US5003362A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit with high-impedance well tie
Assignee: Dallas Semiconductor Corp
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Filing: 1989-07-28
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Granted: 1991-03-26
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Expires: 2009-07-28
Abstract
Abstract An integrated circuit which includes a series resistor in the well tie. This resistor permits the wall to be used for clamping, without large current consumption due to the parastic bipolar device in the well.
Inventors
- 👤 Robert D. Lee
- 👤 Gary V. Zanders
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 01:14
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/211; H10D89/213; H04; H04L; H04L25/00; H04L25/02; H04L25/026
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
138 words
An integrated circuit, comprising: a body including extended portions of monocrystalline semiconductor material, P-type regions of said monocrystalline material extending to the surface of said body in some locations, and N-type regions of said monocrystalline material extending to the surface of said body in other locations; P-channel field-effect transistors, having P-type source/drain regions, being formed in ones of said N-type regions, and N-channel field-effect transistors, having N-type source/drain regions, being formed in ones of said P-type regions; at least one source/drain region of said N-channel transistors being connected to a node which is sought to be clamped, said source/drain region being located in one of said P-type regions which includes a narrow extension thereof and is connected to a reference voltage only through said narrow extension, whereby said narrow extension provides a series resistance to limit clamping current.
Claim 2
Dependent Claim
138 words
An integrated circuit, comprising: a body including extended portions of monocrystalline semiconductor material, P-type regions of said monocrystalline material extending to the surface of said body in some locations, and N-type regions of said monocrystalline material extending to the surface of said body in other locations; P-channel field-effect transistors, having P-type source/drain regions, being formed in ones of said N-type regions, and N-channel field-effect transistors, having N-type source/drain regions, being formed in ones of said P-type regions; at least one source/drain region of said N-channel transistors being connected to a node which is sought to be clamped, said source/drain region being located in one of said P-type regions which includes a narrow extension thereof and is connected to a reference voltage only through said narrow extension, whereby said narrow extension provides a series resistance to limit clamping current.
Claim 3
Dependent Claim
14 words
The integrated circuit of claim 1, wherein said field-effect transistors are metal-gate field-effect transistors.
Claim 4
Dependent Claim
22 words
The integrated circuit of claim 1, wherein said field-effect transistors each have a minimum drawn channel length of at least 6 microns.
Claim 5
Dependent Claim
22 words
The integrated circuit of claim 1, wherein said N-channel and P-channel transistors each have a threshold voltage of at least 1 Volt.
Claim 6
Dependent Claim
23 words
The integrated circuit of claim 1, wherein said field-effect transistors each have an effective channel length L eff of at least 5 microns.
Claim 7
Dependent Claim
22 words
The integrated circuit of claim 1, wherein each of said source/drain regions has a junction depth which is greater than 1.5 microns.
Claim 8
Dependent Claim
28 words
The integrated circuit of claim 1, wherein said field-effect transistors are insulated-gate field-effect transistors, and have a gate dielectric which has a physical thickness greater than 800 Angstroms.
Claim 9
Dependent Claim
29 words
The integrated circuit of claim 1, wherein said field-effect transistors are insulated-gate field-effect transistors, and have a gate dielectric which has a breakdown voltage of at least 30 Volts.
Claim 10
Dependent Claim
31 words
The integrated circuit of claim 1, wherein said field-effect transistors are insulated-gate field-effect transistors, and have a gate dielectric thickness which is equivalent to more than 500 Angstroms of silicon dioxide.
Claim 11
Dependent Claim
45 words
The integrated circuit of claim 1, wherein said field-effect transistors are formed in multiple active areas, and said active areas are separated from each other by a thick field isolation dielectric, and said thick field dielectric has a threshold voltage of less than 10 Volts.
Claim 12
Dependent Claim
16 words
The integrated circuit of claim 1, wherein said extended portions of said body are doped P-type.
Claim 13
Dependent Claim
16 words
The integrated circuit of claim 1, wherein said extended portions of said body are doped N-type.
Claim 14
Dependent Claim
13 words
The integrated circuit of claim 1, wherein said monocrystalline semiconductor material is silicon.
Claim 15
Dependent Claim
25 words
The integrated circuit of claim 1, wherein said extension of said P-type region has a sheet resistance in the range of 300-10000 ohms per square.
Claim 16
Dependent Claim
108 words
The integrated circuit of claim 1, wherein said extended portions of said body are doped P-type, and wherein all of said field-effect transistors are insulated-gate field-effect transistors, and each have a minimum drawn channel length of at least 6 microns, and each have a threshold voltage of at least 1 Volt, and each have an effective channel length L eff of at least 5 microns, and each include respective ones of said source/drain regions with a junction depth which is greater than 1.5 microns, and each have a gate dielectric which has a physical thickness greater than 800 Angstroms and a breakdown voltage of at least 30 Volts.
Claim 17
Dependent Claim
25 words
The integrated circuit of claim 15, wherein said extension of said P-type region has a sheet resistance in the range of 300-10000 ohms per square.
References Cited (Backward Citations)
US4672584A
Cited
US4675561A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-25 | 1994-09-24 | 1995-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-25 | 1998-09-24 | 1999-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-25 | 2002-09-24 | 2003-03-26 | $7700.00 | Window Closed / Lapsed |