US5543360A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a semiconductor device with sidewall etch stopper and wide through-hole having multilayered wiring structure
Assignee: Toshiba Corp
•
Filing: 1995-06-05
•
Granted: 1996-08-06
•
Expires: 2015-06-05
Abstract
Abstract An amorphous silicon layer is formed on the side wall of a first wiring layer having a predetermined wiring width and formed in a predetermined shape by patterning. A silicon oxide layer is covering the first wiring layer and the amorphous silicon layer, and a through-hole is formed in the silicon oxide layer so that a portion of the first wiring layer is exposed. A tungsten layer is filling the through-hole, and a second wiring layer connected to the tungsten layer is formed on the silicon oxide layer.
Inventors
- 👤 Fumitomo Matsuoka
- 👤 Naoki Ikeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:49
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/40; H10W74/481; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/40; H10W20/41; H10W20/42
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
139 words
A method of manufacturing a semiconductor device having a multilayered wiring structure on a semiconductor substrate, comprising the steps of: forming a first insulating layer on said semiconductor substrate; forming a wiring layer having a selected wiring width and a selected shape on said first insulating layer; forming a protection layer on a side wall of said wiring layer; forming a second insulating layer on the entire surface; forming an opening in said second insulating layer having a width equal to or larger than said wiring width of said wiring layer and reaching a surface of said wiring layer by etching, said protection layer serving as a stopper to prevent said first insulating layer from being etched when a formation position of said opening deviates from said wiring layer; and forming a conductive layer connected to said wiring layer.
Claim 2
Independent Claim
139 words
A method of manufacturing a semiconductor device having a multilayered wiring structure on a semiconductor substrate, comprising the steps of: forming a first insulating layer on said semiconductor substrate; forming a wiring layer having a selected wiring width and a selected shape on said first insulating layer; forming a protection layer on a side wall of said wiring layer; forming a second insulating layer on the entire surface; forming an opening in said second insulating layer having a width equal to or larger than said wiring width of said wiring layer and reaching a surface of said wiring layer by etching, said protection layer serving as a stopper to prevent said first insulating layer from being etched when a formation position of said opening deviates from said wiring layer; and forming a conductive layer connected to said wiring layer.
Claim 3
Dependent Claim
61 words
A method according to claim 1, wherein said step of forming said protection layer on a side wall of said wiring layer includes the steps of: forming a silicon layer on the entire surface including said wiring layer; and etching said silicon layer by an anisotropic etching method, leaving said silicon layer on only said side wall of said wiring layer.
References Cited (Backward Citations)
US4561009A
Cited
US4556897A
Cited
EP0119497A1
Cited
US4646126A
Cited
US4582563A
Cited
US4807013A
Cited
US4916521A
Cited
US5036382A
Cited
US4931353A
Cited
US4933303A
Cited
US5286674A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-06 | 2000-02-05 | 2000-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-06 | 2004-02-05 | 2004-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-06 | 2008-02-05 | 2008-08-06 | $7700.00 | Window Closed / Lapsed |