Process for making and programming a flash memory array

Claim 1

A process for fabricating an array of memory cells in a substrate, comprising the steps of: a) forming a raised isolation region on said substrate, said forming step including the steps of: growing a first thermal oxide layer over an active region of said substrate, depositing a first conductive layer over said first thermal oxide used to form floating gates, and depositing a layer of nitride over said first conductive layer; b) masking and etching said first conductive layer and said nitride layer to form a plurality of spaced, elongated stacks extending in a first direction; c) implanting impurities having a conductivity type opposite that of said substrate into the array active area between said stacks to form continuous, elongated diffusion rails extending in said first direction and having a substantially flat contour, said diffusion rails forming spaced bit column lines; d) growing a second thermal oxide layer over said diffusion rails and the edges of said first conductive layer; e) depositing a second conductive layer over said second thermal oxide layer used to form auxiliary gates; f) planarizing said second conductive layer so that it is substantially flush with said nitride layer; g) growing a third thermal oxide layer over said second conductive layer; h) selectively etching said nitride layer to remove portions thereof covering said first conductive layer so as to expose said first conductive layer; i) forming a first dielectric layer over said exposed first conductive layer; j) depositing a third conductive layer over said first dielectric layer; k) depositing a second dielectric layer over said third conductive layer; l) patterning said third conductive layer and said second dielectric layer to form word lines; and m) selectively etching said first conductive layer to substantially align said first conductive layer with said third conductive layer and to form field isolation regions.