Method and apparatus for writing data in a synchronous memory having column independent sections and a method and apparatus for performing write mask operations

Claim 2

A synchronous memory device for storing data, said memory device comprising: a timing and control circuit operable to receive address and control inputs and to generate internal control signals, one of said control inputs comprising a system clock signal operating at a system clock frequency; a memory bank including a plurality of memory sections, each of said memory sections including an array of memory cells arranged in rows and columns; a row decoder coupled to said timing and control circuit and operable to enable rows in each of said memory sections; a column decoder coupled to said timing and control circuit and operable to synchronously enable columns in each of said memory sections substantially simultaneously; and an input buffer coupled to said memory bank, said input buffer operable to receive input data groups at said system clock frequency and to separately latch input data for each of said memory sections in synchronism with said system clock frequency, wherein said input buffer includes a plurality of sets of latches, one each of said sets associated with a respective memory section.

Claim 3

The synchronous memory of device of claim 1, wherein said memory bank comprises an array of dynamic random access memory cells.

Claim 4

The synchronous memory device of claim 1, wherein said memory bank includes two memory sections.

Claim 5

The synchronous memory device of claim 1, wherein each of said sets of latches includes one latch for each data input line coupled to the memory device.

Claim 6

The synchronous memory device of claim 1, wherein said timing and control circuit enables substantially simultaneous writing of data groups into each of said memory sections after each of said sets of latches have latched data to be written.

Claim 7

The synchronous memory device of claim 1, and further comprising a write latch control circuit operable to control said sets of latches such that each set latches that data to be written to said set's respective memory section.

Claim 8

The synchronous memory device of claim 6, wherein said write latch control circuit further comprises: circuitry operable to open each of said sets of latches for the data group to be written to a first memory section; circuitry operable to close the set of latches associated with said first memory section after receiving data for said first memory section and before data for a second memory section is received; and circuitry operable to close the set of latches associated with said second memory section after receiving data for said second memory section.

Claim 9

The synchronous memory device of claim 7, wherein said write latch control circuit further comprises circuitry operable to successively close each respective set of latches after data for each associated memory section is received.

Claim 12

The method of claim 9, further comprising the steps of: opening each of the sets of latches for the data to be written to a first memory section; closing the set of latches associated with the first memory section before data for a second memory section is received; and closing the set of latches associated with the second memory section after receiving data for the second memory section.

Claim 13

The method of claim 10, and further comprising the steps of successively closing each respective set of latches after data for each associated memory section is received.

Claim 14

A synchronous memory device for storing data, said memory device comprising: a timing and control circuit operable to receive address and control inputs and to generate internal control signals, one of said control inputs comprising a system clock signal operating at a system clock frequency; a memory bank including a plurality of memory sections, each of said memory sections including an array of memory cells arranged in rows and columns; a row decoder coupled to said timing and control circuit and operable to enable rows in each of said memory sections; a column decoder coupled to said timing and control circuit and operable to synchronously enable columns in each of said memory sections substantially simultaneously; an input buffer coupled to said memory bank, said input buffer operable to receive data groups at said system clock frequency and to separately latch input data groups for each of said memory sections in synchronism with the system clock frequency; and a write mask circuit operable to mask the writing of data to predetermined memory sections in response to a mask control input, wherein said write mask circuit includes circuitry responsive to said mask control input and a section select signal, said section select signal indicating which memory section is to be masked, such that writing is prevented to the memory section to be masked upon assertion of said mask control input.

Claim 15

A synchronous memory device for storing data, said memory device comprising: a timing and control circuit operable to receive address and control inputs and to generate internal control signals, one of said control inputs comprising a system clock signal operating at a system clock frequency; a memory bank including a plurality of memory sections, each of said memory sections including an array of memory cells arranged in rows and columns; a row decoder coupled to said timing and control circuit and operable to enable rows in each of said memory sections; a column decoder coupled to said timing and control circuit and operable to synchronously enable columns in each of said memory sections substantially simultaneously; an input buffer coupled to said memory bank, said input buffer operable to receive data groups at said system clock frequency and to separately latch input data groups for each of said memory sections in synchronism with the system clock frequency; and a write mask circuit operable to mask the writing of data to predetermined memory sections in response to a mask control input, wherein said write mask circuit includes circuitry responsive to said mask control input and a section select signal, said section select signal indicating which memory section is to be masked, such that writing is prevented to the memory section to be masked upon assertion of said mask control input.

Claim 16

The synchronous memory of device of claim 12, wherein said memory bank comprises an array of dynamic random access memory cells.

Claim 17

The synchronous memory device of claim 12, wherein said memory bank includes two memory sections.

Claim 18

The synchronous memory device of claim 12, wherein said memory bank includes two memory sections, and wherein said section select signal, when active, toggles between said two memory sections at said system clock frequency.

Claim 21

The method of claim 16, wherein said step of masking further comprises the steps of: receiving a mask control signal synchronously with the data group to be masked; selecting the memory section that corresponds to the address of the data group to be masked; and preventing the writing of data to the memory section that corresponds to the address of the data to be masked.