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US5539349A
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Method and apparatus for post-fabrication ascertaining and providing programmable precision timing for sense amplifiers and other circuits
Assignee: Renesas Technology America Inc
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Filing: 1994-03-24
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Granted: 1996-07-23
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Expires: 2014-03-24
Abstract
Abstract The present invention includes a variable delay element that can be programmed by a combination of control signals whose values may be determined by a matrix of programming elements, preferably fuses. In a TEST mode, a multiplexer array decouples the matrix, and instead couples a combination of user provided TEST mode control signals to the variable delay element. TEST mode permits selection of a suitable delay by observing the effect on IC functionality of all available values of delay provided by these TEST mode user-provided control signals. Once a suitable delay has been determined, the matrix may be programmably altered to permanently store and provide to the variable delay element the appropriate pattern of control signals to produce such delay.
Inventors
- 👤 Richard S. Roy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:23
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/26; H03H11/265
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
125 words
An on-chip circuit for determining and maintaining a delay between an input signal and an output signal, comprising: variable delay means, coupled to receive the input signal and at least one programmable delay control signal, for providing after a time delay a delayed version of said input signal as said output signal, said delay determined by said at least one programmable delay control signal; and programming means, coupled to said variable delay means, including means for maintaining said programmable delay control signal in response to at least one programming input signal, said programmable delay control signal fixing said delay and said on-chip circuit being fabricated on an integrated circuit chip that includes at least one circuit coupled to and responsive to said delayed output signal.
Claim 2
Dependent Claim
125 words
An on-chip circuit for determining and maintaining a delay between an input signal and an output signal, comprising: variable delay means, coupled to receive the input signal and at least one programmable delay control signal, for providing after a time delay a delayed version of said input signal as said output signal, said delay determined by said at least one programmable delay control signal; and programming means, coupled to said variable delay means, including means for maintaining said programmable delay control signal in response to at least one programming input signal, said programmable delay control signal fixing said delay and said on-chip circuit being fabricated on an integrated circuit chip that includes at least one circuit coupled to and responsive to said delayed output signal.
Claim 3
Dependent Claim
28 words
The circuit of claim 1, wherein said programming means includes a matrix of m programmable elements, each said element capable of maintaining a logical "0" or "1" state.
Claim 4
Dependent Claim
25 words
The circuit of claim 2, further including logic means for logically coupling said programmable elements to produce 2 m combinations of said programming input signals.
Claim 5
Dependent Claim
28 words
The circuit of claim 2, wherein said elements are user blowable fuses, select ones of which are blown to produce said chosen one of a plurality of combinations.
Claim 6
Dependent Claim
78 words
The circuit of claim 2, wherein said programming means further includes multiplex means, coupled to said matrix of m elements and coupled to said variable - delay means, for decoupling, upon receipt of a TEST mode signal, said matrix of m elements from said variable delay means and for coupling to said variable delay means one or more user provided input signals; wherein during said TEST mode signal, said delay is determined by said user provided input signals.
Claim 7
Dependent Claim
71 words
The circuit of claim 1, wherein said variable - delay means includes at least a first delay-producing pair of inverter transistors, and at least one transmission gate for selectively bypassing said delay-producing pair; wherein said input signal passes through said first delay-producing pair and appears as said output signal in a first time delay state, and wherein said input signal bypasses said first delay-producing pair in a second time delay state.
Claim 8
Dependent Claim
43 words
The circuit of claim 6, further including a delay-altering transistor switchably coupled in parallel to a transistor in said first delay-producing pair, said delay-altering transistor responding to a said programming input signal to alter a time delay produced by said first delay-producing pair.
Claim 9
Dependent Claim
16 words
The circuit of claim 1, wherein said at least one circuit includes a memory sense amplifier.
Claim 10
Independent Claim
147 words
A method for determining and maintaining a delay between an input signal on an integrated circuit chip and an output signal on the integrated circuit chip said chip including at least one circuit coupled to and responsive to said delayed output signal, the method comprising the following steps: providing variable delay means on said integrated circuit chip, coupled to receive the input signal and at least one programmable delay control signal, for providing after a time delay a delayed version of said input signal as said output signal, said delay being determined by said at least one programmable delay control signal; providing programming means on said integrated circuit chip, coupled to said variable delay means, for maintaining said programmable delay control signal in response to at least one programming input signal, said programmable delay control signal fixing said delay of said output signal to said responsive circuit.
Claim 11
Independent Claim
147 words
A method for determining and maintaining a delay between an input signal on an integrated circuit chip and an output signal on the integrated circuit chip said chip including at least one circuit coupled to and responsive to said delayed output signal, the method comprising the following steps: providing variable delay means on said integrated circuit chip, coupled to receive the input signal and at least one programmable delay control signal, for providing after a time delay a delayed version of said input signal as said output signal, said delay being determined by said at least one programmable delay control signal; providing programming means on said integrated circuit chip, coupled to said variable delay means, for maintaining said programmable delay control signal in response to at least one programming input signal, said programmable delay control signal fixing said delay of said output signal to said responsive circuit.
Claim 12
Dependent Claim
32 words
The method of claim 9, wherein said step of providing programming means includes providing a matrix of m programmable elements, each said element capable of maintaining a logical "0" or "1" state.
Claim 13
Dependent Claim
25 words
The method of claim 10, further including the step of logically coupling said programmable elements to produce 2 m combinations of said programming input signals.
Claim 14
Dependent Claim
29 words
The method of claim 10, wherein said programmable elements are user blowable fuses, select ones of which are blown to produce said chosen one of a plurality of combinations.
Claim 15
Dependent Claim
51 words
The method of claim 9, wherein said integrated circuit chip requires at least two different time delays, and wherein said step of providing variable delay means includes providing at least two said variable delay means, and wherein said step of providing programming means includes providing at least one said programming means.
Claim 16
Dependent Claim
78 words
The method of claim 9, wherein said step of providing programming means further includes providing multiplex means, coupled to said variable delay means, for decoupling, upon receipt of a TEST mode signal, said means for maintaining from said variable delay means and for coupling to said variable delay means a plurality of user provided combinations of programming input signals; wherein during said TEST mode signal, said delay is determined by said user provided combinations of programming input signals.
Claim 17
Dependent Claim
71 words
The method of claim 9, wherein said variable - delay means includes at least a first delay-producing pair of inverter transistors, and at least one transmission gate for selectively bypassing said delay-producing pair; wherein said input signal passes through said first delay-producing pair and appears as said output signal in a first time delay state, and wherein said input signal bypasses said first delay-producing pair in a second time delay state.
Claim 18
Dependent Claim
47 words
The method of claim 15, wherein said variable delay means includes a delay-altering transistor switchably coupled in parallel to a transistor in said first delay-producing pair, said delay-altering transistor responding to a said programming input signal to alter a time delay produced by said first delay-producing pair.
Claim 19
Dependent Claim
41 words
The method of claim 9, including the additional step of providing said integrated circuit chip with metallization default programming means, coupled to said variable delay means, for programming a time delay according to a metallization pattern on said integrated circuit chip.
Claim 20
Dependent Claim
62 words
The method of claim 17, wherein said metallization default programming means is programmed according to a criterion selected from the list consisting of (a) minimizing programming required during said step of providing programming means, and (b) providing a default time delay that matches a delay actually required by a substantial number of mass-produced said integrated circuit chips according to actual historical data.
Claim 21
Dependent Claim
25 words
The method of claim 9, wherein said circuit on said integrated circuit chip includes at least one sense amplifier coupled to receive said output signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-23 | 2000-01-22 | 2000-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-23 | 2004-01-22 | 2004-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-23 | 2008-01-22 | 2008-07-23 | $7700.00 | Window Closed / Lapsed |