Method and apparatus for improving fault coverage of system logic of an integrated circuit with embedded memory arrays

Claim 3

The apparatus of claim 1, wherein said binary constant generator/selector comprises: a plurality of multiplexers, each coupled to one of a plurality of output lines of said memory array and to a binary constant signal source, said plurality of multiplexors outputting operational data provided along said output lines of said memory array during said normal mode of operation, and said binary constant during said test mode of operation.

Claim 4

The apparatus of claim 1, wherein said binary constant generator/selector comprises: a first plurality of multiplexors, each coupled to one of a first plurality of output lines of said memory array and to a 1-bit signal source, said first plurality of multiplexors outputting a first portion of said operational data during said normal mode of operation, and said 1-bit signals during said test mode of operation; and a second plurality of multiplexors, each coupled to one of a second plurality of output lines of said memory array and to a 0-bit source for outputting a second portion of said operational data during said normal mode of operation, and 0-bit signals during said test mode of operation.

Claim 5

The apparatus of claim 1, wherein said binary constant generator/selector comprises: a first mode controller outputting a 0-bit during said normal mode of operation and a 1-bit during said test mode of operation; a plurality of OR gates each coupled to said first mode controller and to one of a first plurality of output lines of said memory array, said first plurality of OR gates collectively outputting a first portion of said operational data during said normal mode of operation and outputting 1-bits during said test mode of operation; and a second mode controller outputting a 1-bit during said normal mode of operation and a 0-bit during said test mode of operation; and a plurality of AND gates each coupled to said second controller and to one of a second plurality of output lines of said memory array, said plurality of AND gates collectively outputting a second portion of said operational during said normal mode of operation and 0-bits during said test mode of operation.

Claim 6

The apparatus of claim 1, wherein said binary constant generator/selector comprises: a first mode controller outputting a 1-bit during said normal mode of operation and a 0-bit during said test mode of operation; a plurality of NAND gates each coupled to said first mode controller and to one of a first plurality of output lines of said memory array, said plurality of NAND gates collectively outputting the complement of a first portion of said operational data during said normal mode of operation and the complement of 0-bits during said test mode of operation; a second mode controller outputting a 0-bit during said normal mode of operation and a 1-bit during said test mode of operation; and a plurality of NOR gates each coupled to said second mode controller and to one of a second plurality of output lines of said memory array, said plurality of NOR gates collectively outputting the complement of a second portion of said operational data during said normal mode of operation and the complement of 1-bits during said test mode of operation.

Claim 7

The integrated circuit of claim 1, wherein said memory array, said binary constant generator/selector and said system logic circuitry are all formed within a single integrated circuit.

Claim 8

The apparatus of claim 1, wherein said binary constant generator/selector comprises a set of output latches, coupled to said memory array, said latches outputting said operational data during said normal mode of operation and said predetermined binary constant during said test mode of operation.

Claim 9

The apparatus of claim 7, wherein said set of output latches comprises: a first and a second plurality of output latch elements, each coupled to one of a first and second plurality of output lines of said memory array, said first and second plurality of output latch elements collectively outputting respective first and second portions of said operational data; a plurality of n-channel transistors each having a drain coupled to an output of a respective one of said first plurality of latch elements, a gate connected to said test enable input line, and a source connected to a low voltage source; and a plurality of p-channel transistors each having a source coupled to an output of a respective one of said second plurality of latch elements, a gate connected to said test enable input line, and a drain connected to a high voltage source.

Claim 10

The apparatus of claim 1, wherein said binary constant generator/selector comprises: a plurality of transistor-based 1-bit generator elements each coupled to one of a first plurality of output lines of said memory array, said 1-bit generator elements collectively outputting a first portion of said operation data during said normal mode of operation and 1-bits during said test mode of operation; and a plurality of transistor-based 0-bit generator elements each coupled to one of a second plurality of output lines of said memory array, said 0-bit generator elements collectively outputting a second portion of said operational data during said normal mode of operation and 0-bits during said test mode of operation.

Claim 11

The apparatus of claim 9, wherein each of said transistor based 1-bit generator elements comprises: a first p-channel transistor having a source, a gate and a drain; a first n-channel transistor having a drain connected to said drain of said p-channel transistor, a gate and a source connected to a low voltage source, with said gates of said first p-channel transistor and said first n-channel transistor both connected to a respective one of said first plurality of output lines of said memory array; a second p-channel transistor having a source, a gate and a drain; a second n-channel transistor having a drain connected to said source of said first p-channel transistor, a gate and a drain connected to said low voltage source, with said gates of said second p-channel transistor and said second n-channel transistor both connected to said drain of said first p-channel transistor; and a third p-channel transistor having a source connected to a high voltage, a gate connected to said test enable input line, and a drain connected to said drain of said first p-channel transistor.

Claim 12

The apparatus of claim 9, wherein said transistor-based 0-bit generator elements each comprises: a first p-channel transistor having a source, a gate and a drain; a first n-channel transistor having a drain connected to said drain of said p-channel transistor, a gate, and a source connected to a low voltage source, with said gates of said first p-channel transistor and said first n-channel transistor both connected to a respective one of said second plurality of output lines of said memory array; a second p-channel transistor having a source, a gate and a drain; a second n-channel transistor having a drain connected to said source of said first p-channel transistor, a gate, and a source connected to said low voltage source, with said gates of said second p-channel transistor and said second n-channel transistor both connected to said drain of said first p-channel transistor; and a third p-channel transistor having a source connected to said drain of said first p-channel transistor, a gate connected to said test enable input line, and a drain connected to said drain of said first n-channel transistor and to said low voltage source.

Claim 13

The apparatus of claim 1, wherein said memory array includes memory cells and wherein said binary constant generator/selector comprises: a first plurality of differential amplifiers each coupled to one of a first plurality of output lines of said memory cells, said first plurality of differential amplifiers collectively outputting a first portion of operational data from said memory cells during said normal mode of operation and 1-bits during said test mode of operation; and a second plurality of differential amplifiers each coupled to one of a second plurality of output lines of said memory cells, said second plurality of differential amplifiers collectively outputting a second portion of said operational data during said normal mode of operation and 0-bits during said test mode of operation.

Claim 14

The apparatus in claim 12, each of said first plurality of differential amplifiers comprises: a first n-channel transistor having a drain, a gate connected to an output of a respective one of said memory cells, and a source connected to a low voltage source; a first p-channel transistor having a source connected to a high voltage source, a gate, a drain connected to said drain of said first n-channel transistor; a second p-channel transistor having a source connected to said high voltage, a gate connected to said gate of said first p-channel transistor and to said drain of said first n-channel transistor and a drain connected to an output line; a second n-channel transistor having a drain connected to said drain of said second p-channel transistor and to said output line, a gate connected to an inverted input from said respective memory cell, a source connected to said low voltage; a third p-channel transistor having a source connected to said high voltage, a gate connected to said test enable input, and a drain connected to said output line.

Claim 15

The apparatus of claim 13, wherein each of said second plurality of differential amplifiers comprises: a first n-channel transistor having a drain, a gate connected to an output of a respective one of said memory cells, and a source connected to a low voltage source; a first p-channel transistor having a drain connected to a high voltage source, a gate, a drain connected to said source of said first n-channel transistor; a second p-channel transistor having a source connected to said high voltage, a gate connected to said gate of said first p-channel transistor and to said drain of said first n-channel transistor and a drain connected to an output line; a second n-channel transistor having a drain connected to said drain of said second p-channel transistor and to said output line, a gate connected to an inverted input from said respective memory cell, a source connected to said low voltage; a third n-channel transistor having a drain connected to said output line, a gate connected to said test enable input, and a source connected to said low voltage.

Claim 16

An integrated circuit comprising: an embedded memory array storing and outputting operational data; a first plurality of multiplexors, each coupled to one of a first plurality of output lines of said memory array, to a 1-bit signal source and to a test enable input, said first plurality of multiplexors outputting a first portion of said operational data during a normal mode of operation identified by said test enable input being in a first state, and outputting said 1-bit signals during a test mode of operation identified by said test enable signal being in a second state; a second plurality of multiplexors, each coupled to one of a second plurality of output lines of said memory array, to a 0-bit source and to said test enable input for outputting a second portion of said operational data during said normal mode of operation, and 0-bit signals during said test mode of operation; and system logic circuitry, coupled to said first and second plurality of multiplexors, for processing said operational data, said system logic circuitry receiving said 0-bit signals and set 1-bit signals during said test mode of operation in a permanent arrangement that represents a fixed value, and receiving said first and second portion of operational data during said normal mode of operation.

Claim 17

An integrated circuit comprising: an embedded memory array storing and outputting operational data; a first plurality of multiplexors, each coupled to one of a first plurality of output lines of said memory array, to a 1-bit signal source and to a test enable input, said first plurality of multiplexors outputting a first portion of said operational data during a normal mode of operation identified by said test enable input being in a first state, and outputting said 1-bit signals during a test mode of operation identified by said test enable signal being in a second state; a second plurality of multiplexors, each coupled to one of a second plurality of output lines of said memory array, to a 0-bit source and to said test enable input for outputting a second portion of said operational data during said normal mode of operation, and 0-bit signals during said test mode of operation; and system logic circuitry, coupled to said first and second plurality of multiplexors, for processing said operational data, said system logic circuitry receiving said 0-bit signals and set 1-bit signals during said test mode of operation in a permanent arrangement that represents a fixed value, and receiving said first and second portion of operational data during said normal mode of operation.

Claim 20

The method of claim 16, wherein said step of providing a binary constant generator/selector comprises the steps of: providing a plurality of multiplexors, each coupled to one of a plurality of output lines of said memory array and to a binary constant signal source, for performing the step of outputting operational data provided along said output lines of said memory array during said normal mode of operation, and outputting said binary constant during said test mode of operation.

Claim 21

The method of claim 16, wherein said step of providing a binary constant generator/selector comprises the steps of: providing a first plurality of multiplexors, each coupled to one of a first plurality of output lines of said memory array and to a 1-bit signal source, for performing the step of outputting a first portion of said operational data during said normal mode of operation, and outputting said 1-bit signals during said test mode of operation; and providing a second plurality of multiplexors, each coupled to one of a second plurality of output lines of said memory array and to a 0-bit source for performing the step of outputting a second portion of said operational data during said normal mode of operation, and outputting 0-bit signals during said test mode of operation.

Claim 22

The method of claim 16, wherein said step of providing a binary constant generator/selector comprises the step of: providing a first mode controller for performing the step of outputting a 0-bit during said normal mode of operation and a 1-bit during said test mode of operation; providing a plurality of OR gates each coupled to said first mode controller and to one of a first plurality of output lines of said memory array, collectively for performing the step of outputting a first portion of said operational data during said normal mode of operation and outputting 1-bits during said test mode of operation; providing a second mode controller for performing the step of outputting a 1-bit during said normal mode of operation and a 0-bit during said test mode of operation; and providing a plurality of AND gates each coupled to said second controller and to one of a second plurality of output lines of said memory array, for performing the step of collectively outputting a second portion of said operational during said normal mode of operation and 0-bits during said test mode of operation.

Claim 23

The method of claim 16, wherein said step of providing a binary constant generator/selector comprises the steps of the step of: providing a first mode controller for performing the step of outputting a 1-bit during said normal mode of operation and a 0-bit during said test mode of operation; providing a plurality of NAND gates each coupled to said first mode controller and to one of a first plurality of output lines of said memory array, for performing the step of collectively outputting the complement of a first portion of said operational data during said normal mode of operation and the complement of 0-bits during said test mode of operation; providing a second mode controller for performing the step of outputting a 0-bit during said normal mode of operation and a 1-bit during said test mode of operation; and providing a plurality of NOR gates each coupled to said second mode controller and to one of a second plurality of output lines of said memory array, said plurality of NOR gates collectively outputting the complement of a second portion of said operational data during said normal mode of operation and the complement of 1-bits during said test mode of operation.

Claim 24

The method of claim 16, wherein said step of providing binary constant generator/selector comprises the steps of: providing a plurality of transistor-based 1-bit generator elements each coupled to one of a first plurality of output lines of said memory array, for performing the step of collectively outputting a first portion of said operational data during said normal mode of operation and 1-bits during said test mode of operation; and providing a plurality of transistor-based 0-bit generator elements each coupled to one of a second plurality of output lines of said memory array, for performing the step of collectively outputting a second portion of said operational data during said normal mode of operation and 0-bits during said test mode of operation.

Claim 25

The method of claim 21, wherein said step of providing said transistor based 1-bit generator elements comprises the steps of: providing a first p-channel transistor having a source, a gate and a drain; providing a first n-channel transistor having a drain connected to said drain of said p-channel transistor, a gate and a source connected to a low voltage source, with said gates of said first p-channel transistor and said first n-channel transistor both connected to a respective one of said first plurality of output lines of said memory array; providing a second p-channel transistor having a source, a gate and a drain; providing a second n-channel transistor having a drain connected to said source of said first p-channel transistor, a gate and a source connected to said low voltage source, with said gates of said second p-channel transistor and said second n-channel transistor both connected to said drain of said first p-channel transistor; and providing a third p-channel transistor having a source connected to a high voltage, a gate connected to said test enable input line, and a drain connected to said drain of said first p-channel transistor.

Claim 26

The method of claim 21, wherein said step of providing transistor-based 0-bit generator elements comprises the steps of: providing a first p-channel transistor having a source, a gate and a drain; providing a first n-channel transistor having a drain connected to said drain of said p-channel transistor, a gate, and a source connected to a low voltage source, with said gates of said first p-channel transistor and said first n-channel transistor both connected to a respective one of said second plurality of output lines of said memory array; providing a second p-channel transistor having a source, a gate and a drain; providing a second n-channel transistor having a drain connected to said source of said first p-channel transistor, a gate, and a source connected to said low voltage source, with said gates of said second p-channel transistor and said second n-channel transistor both connected to said drain of said first p-channel transistor; and providing a third p-channel transistor having a source connected to said drain of said first p-channel transistor, a gate connected to said test enable input line, and a drain connected to said source of said first n-channel transistor and to said low voltage source.

Claim 27

The method of claim 16, wherein the step of providing each of said second plurality of differential amplifiers comprises: providing a first n-channel transistor having a drain, a gate connected to an output of a respective one of said memory cells, and a source connected to a low voltage source; providing a first p-channel transistor having a source connected to a high voltage source, a gate, a drain connected to said drain of said first n-channel transistor; providing a second p-channel transistor having a source connected to said high voltage, a gate connected to said gate of said first p-channel transistor and to said drain of said first n-channel transistor and a drain connected to an output line; providing a second n-channel transistor having a drain connected to said drain of said second p-channel transistor and to said output line, a gate connected to an inverted input from said respective memory cell, and a source connected to said low voltage; providing a third n-channel transistor having a drain connected to said output line, a gate connected to said test enable input, and a source connected to said low voltage.

Claim 28

The method of claim 16, wherein said step of providing binary constant generator/selector comprises the steps of: providing a set of output latches, coupled to said memory array for performing the step of outputting said operational data during said normal mode of operation and said predetermined binary constant during said test mode of operation.

Claim 29

The method of claim 25, wherein said step of providing set of output latches comprises the steps of: providing a first and a second plurality of output latch elements, each coupled to one of a first and second plurality of output lines of said memory array, for performing the step of collectively outputting respective first and second portions of said operational data; a plurality of n-channel transistors each having a drain coupled to an output of a respective one of said first plurality of latch elements, a gate connected to said test enable input line, and a source connected to a low voltage source; and a plurality of p-channel transistors each having a source coupled to an output of a respective one of said second plurality of latch elements, a gate connected to said test enable input line, and a drain connected to a high voltage source.

Claim 30

The method of claim 16, wherein said memory array includes memory cells and wherein said step of providing binary constant generator/selector comprises: providing a first plurality of differential amplifiers each coupled to one of a first plurality of output lines of said memory cells, for performing the step of collectively outputting a first portion of operational data from said memory cells during said normal mode of operation and 1-bits during said test mode of operation; and providing a second plurality of differential amplifiers each coupled to one of a second plurality of output lines of said memory cells, for performing the step of collectively outputting a second portion of said operational data during said normal mode of operation and 0-bits during said test mode of operation.

Claim 31

The method in claim 27, providing each of said first plurality of differential amplifiers comprises: providing a first n-channel transistor having a drain, a gate connected to an output of a respective one of said memory cells, and a source connected to a low voltage source; providing a first p-channel transistor having a source connected to a high voltage source, a gate, a drain connected to said drain of said first n-channel transistor; providing a second p-channel transistor having a source connected to said high voltage, a gate connected to said gate of said first p-channel transistor and to said drain of said first n-channel transistor and a drain connected to an output line; providing a second n-channel transistor having a drain connected to said drain of said second p-channel transistor and to said output line, a gate connected to an inverted input from said respective memory cell, a source connected to said low voltage; providing a third p-channel transistor having a source connected to said high voltage, a gate connected to said test enable input, and a drain connected to said output line.