Patent US5539324A successfully refreshed from Google Patents.
US5539324A
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Universal wafer carrier for wafer level die burn-in
Assignee: Micron Technology Inc
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Filing: 1992-11-24
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Granted: 1996-07-23
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Expires: 2012-11-24
Abstract
Abstract A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical test equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical test are completed. After burn-in stress and electrical test, it is possible to establish interconnection between the single dice or separate and package the dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
Inventors
- 👤 Alan G. Wood
- 👤 Tim J. Corbett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:51
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/68; G; G01; G01R; G01R1/00; G01R1/02; G01R1/04; G01R1/0408; G01R1/0491; H10P; H10P74/00; H10P74/23; H10W99/00; G01R31/00; G01R31/28; G01R31/282; G01R31/2831; G01R31/2851; G01R31/2855; G01R31/286; G01R31/2863; G01R31/2865; G01R31/2867; G01R31/2886; G01R31/2889; H05; H05K; H05K2201/00; H05K2201/01; H05K2201/0104; H05K2201/0133; H05K2201/03; H05K2201/0332; H05K2201/0335; H05K2201/0347; H05K2201/0364; H05K2201/0367; H05K2201/0388; H05K2201/0394; H05K2201/09; H05K2201/09209; H05K2201/09372; H05K2201/09481; H05K2201/095; H05K2201/09563; H05K2203/00; H05K2203/03; H05K2203/0307; H05K2203/07; H05K2203/0703; H05K2203/0723; H05K3/00; H05K3/0058; H05K3/0067; H05K3/40; H05K3/42; H05K3/423; H10W70/681; H10W90/00; H10W90/20; H10W90/24; H10W90/701; H10W90/721; H10W90/722
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
179 words
Wafer testing apparatus for testing a plurality of semiconductor devices contained on a wafer comprising: a) a first plate; b) a wafer-receiving means in the first plate for receiving the wafer; c) a second plate mating with the first plate; d) alignment means for aligning the first plate with the second plate; e) a plurality of contact tips extending from the second plate; f) the contact tips being positioned so that, when the first plate and the second plate are aligned by the alignment means and the wafer is positioned in the wafer-receiving means, the contact tips are in alignment with contact locations on the wafer; g) connector terminals electrical communication with the contact tips, the connector terminals being mounted to one of said plates; and h) a floating platform mounted to the first plate opposite to the contact tips and in a position for supporting the wafer for travel in the assembled testing apparatus for pressing the wafer towards the contact tips to establish an electrical connection between the contact tips and the contact locations on the wafer.
Claim 2
Dependent Claim
179 words
Wafer testing apparatus for testing a plurality of semiconductor devices contained on a wafer comprising: a) a first plate; b) a wafer-receiving means in the first plate for receiving the wafer; c) a second plate mating with the first plate; d) alignment means for aligning the first plate with the second plate; e) a plurality of contact tips extending from the second plate; f) the contact tips being positioned so that, when the first plate and the second plate are aligned by the alignment means and the wafer is positioned in the wafer-receiving means, the contact tips are in alignment with contact locations on the wafer; g) connector terminals electrical communication with the contact tips, the connector terminals being mounted to one of said plates; and h) a floating platform mounted to the first plate opposite to the contact tips and in a position for supporting the wafer for travel in the assembled testing apparatus for pressing the wafer towards the contact tips to establish an electrical connection between the contact tips and the contact locations on the wafer.
Claim 3
Dependent Claim
31 words
Wafer testing apparatus as described in claim 1 and wherein: the platform is mounted in a wafer-receiving cavity formed in the first plate, and is in contact with an elastomeric polymer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-23 | 2000-01-22 | 2000-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-23 | 2004-01-22 | 2004-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-23 | 2008-01-22 | 2008-07-23 | $7700.00 | Window Closed / Lapsed |