US5539243A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having spaces and having reduced parasitic capacitance
Assignee: NEC Electronics Corp
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Filing: 1994-08-03
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Granted: 1996-07-23
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Expires: 2014-08-03
Abstract
Abstract A semiconductor device containing a first electrode formed under an interlayer insulator film and a second electrode formed on or over the interlayer insulator film. The first electrode is connected to an active region formed at a semiconductor substrate. The second electrode acts as a bonding pad and is connected to the first electrode through the interlayer insulator film. Between the second electrode and the substrate, there is a capacitance-reduction structure composed of an insulator layer having a plurality of hollow spaces arranged at intervals. Due to the capacitance-reduction structure, the dielectric material existing between the second electrode and the substrate contains the hollow spaces therein, resulting in a reduced parasitic capacitance produced using the second electrode, substrate and the dielectric material.
Inventors
- 👤 Junichi Matsuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:01
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/482; H10W20/484; H10W20/495; H10W72/00; H10W72/90; H10W72/931; H10W72/934
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
162 words
A semiconductor device comprising: (a) a semiconductor substrate having an active region; (b) a first electrode formed in a first level, said first level being placed over said substrate, said first electrode being electrically connected to said active region; (c) an interlayer insulator film formed in a second level, said second level being higher than said first level, said interlayer insulator film covering said first electrode and having an opening; and (d) a second electrode formed in a third level, said third level being higher than said second level, said second electrode acting as a bonding pad and being electrically connected to said first electrode through said opening of said interlayer insulator film; wherein said interlayer insulator film has a plurality of hollow spaces arranged laterally at intervals between said second electrode and said substrate; and wherein a parasitic capacitance produced by said second electrode and said substrate is reduced by said spaces because no insulator material is filled into said spaces.
Claim 2
Dependent Claim
162 words
A semiconductor device comprising: (a) a semiconductor substrate having an active region; (b) a first electrode formed in a first level, said first level being placed over said substrate, said first electrode being electrically connected to said active region; (c) an interlayer insulator film formed in a second level, said second level being higher than said first level, said interlayer insulator film covering said first electrode and having an opening; and (d) a second electrode formed in a third level, said third level being higher than said second level, said second electrode acting as a bonding pad and being electrically connected to said first electrode through said opening of said interlayer insulator film; wherein said interlayer insulator film has a plurality of hollow spaces arranged laterally at intervals between said second electrode and said substrate; and wherein a parasitic capacitance produced by said second electrode and said substrate is reduced by said spaces because no insulator material is filled into said spaces.
Claim 3
Dependent Claim
54 words
A semiconductor device as claimed in claim 1, further comprising a patterned field insulator film formed on said substrate; wherein said field insulator film is disposed between said substrate and said first level, and has holes penetrating to said substrate; and wherein said spaces of said interlayer insulator film are formed in said holes.
Claim 4
Dependent Claim
33 words
A semiconductor device as claim 2, wherein said field insulator film is placed in a depression of said substrate; and wherein said spaces of said interlayer insulator film are disposed in said depression.
Claim 5
Dependent Claim
18 words
A semiconductor device as claimed in claim 1, wherein all of said spaces are isolated from each other.
Claim 6
Dependent Claim
18 words
A semiconductor device as claimed in claim 1, wherein said spaces laterally extend in parallel along a direction.
References Cited (Backward Citations)
JPS5239378A
Cited
JPS644029A
Cited
JPS6474731A
Cited
EP0340727A2
Cited
JPH0396243A
Cited
US5189505A
Cited
GB2243485A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-23 | 2000-01-22 | 2000-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-23 | 2004-01-22 | 2004-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-23 | 2008-01-22 | 2008-07-23 | $7700.00 | Window Closed / Lapsed |