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JPH0396243A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated circuit device

Assignee: Seiko Epson Corp
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Filing: 1989-09-08
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Granted: —
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Expires: 2009-09-08
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Abstract

Abstract PURPOSE:To incorporate more bonding pads in the same chip size by providing steps on the surface of a bonding pad of a range in contact with an outer signal line. CONSTITUTION:Steps 10 are provided on the surface of a bonding pad 1 of a range in which a lead connecting electrode (bonding pad) 1 for transmitting a signal to an exterior or receiving a signal from the exterior is brought into contact with an outer signal line in a semiconductor integrated circuit device. For example, a polycrystalline silicon 2 is laid on the lower layer of the pad 1, holes 3 exist on the silicon 2, and the silicon 2 laid on the lower layer and the steps 10 due to the influence of the shape of the holes 3 are formed on the pad 1. Thus, contact area can be increased in the same range. Thus, the contact resistance of the signal line with the pad can be reduced, and adhering strength can be increased.

Inventors

  • 👤 Takashi Sakuta
  • 👤 孝 作田

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 17:55
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10W70/00; H10W70/60; H10W72/071; H10W72/075; H10W72/07551; H10W72/07553; H10W72/50; H10W72/531; H10W72/536; H10W72/59; H10W72/931; H10W72/934; H10W72/981; H10W72/983

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