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Planarized semiconductor structure with subminimum features

Assignee: International Business Machines Corp
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Filing: 1995-06-06
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Granted: 1996-07-23
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Expires: 2015-06-06
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Abstract

Abstract Improved, planarized semiconductor structures are described which are prepared by a method involving the creation of a series of subminimum (i.e., 50 to 500 angstroms thick) polysilicon pillars extending vertically upward from the base of a wide trench and depositing a conductor material by chemical vapor deposition over the pillars; the pillars prevent the formation of a depression within the trench when planarized.

Inventors

  • 👤 John E. Cronin
  • 👤 Howard S. Landis

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 21:10
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/69; H10P50/691; H10P50/692; H10P95/00; H10P95/06; H10P95/062; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/945

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 92 words
A planarized semiconductor structure comprising: a recessed area within the structure, having a surface adjacent said recessed area; a plurality of pillars formed within said recessed area; a planarized layer of fill which comprises a conductor material or a semiconductor material, deposited over said pillars and said recessed area, wherein a second surface of said planarized layer of fill is substantially planar with said surface of said semiconductor structure, and wherein the grain boundaries of the material forming the pillars is distinct from the grain boundaries of the conductor or semiconductor material.
Claim 2
Dependent Claim 92 words
A planarized semiconductor structure comprising: a recessed area within the structure, having a surface adjacent said recessed area; a plurality of pillars formed within said recessed area; a planarized layer of fill which comprises a conductor material or a semiconductor material, deposited over said pillars and said recessed area, wherein a second surface of said planarized layer of fill is substantially planar with said surface of said semiconductor structure, and wherein the grain boundaries of the material forming the pillars is distinct from the grain boundaries of the conductor or semiconductor material.
Claim 3
Dependent Claim 14 words
The planarized semiconductor structure of claim 1, wherein said conductor material comprises a metal.
Claim 4
Dependent Claim 19 words
The planarized semiconductor structure of claim 2, wherein the conductor material for the fill layer comprises a metal silicide.
Claim 5
Dependent Claim 21 words
The planarized semiconductor structure of claim 1 wherein the density of said pillars comprises one to ten pillars per square micron.
Claim 6
Dependent Claim 13 words
The planarized semiconductor structure of claim 1 wherein said pillars are randomly placed.
Claim 7
Dependent Claim 14 words
The planarized semiconductor structure of claim 1 wherein said recessed area comprises a trench.
Claim 8
Dependent Claim 17 words
The planarized semiconductor of claim 1, wherein the pillars are formed of a material comprising a conductor.
Claim 9
Dependent Claim 18 words
The planarized semiconductor structure of claim 7, wherein the conductor used to form the pillars comprises a metal.
Claim 10
Dependent Claim 17 words
The planarized semiconductor structure of claim 1, wherein the pillars are form of a material comprising polysilicon.
Claim 11
Dependent Claim 13 words
The planarized semiconductor structure of claim 1 wherein said pillars are non-randomly placed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-07-23 2000-01-22 2000-07-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-07-23 2004-01-22 2004-07-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-07-23 2008-01-22 2008-07-23 $7700.00 Window Closed / Lapsed

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