Patent NL7515014A successfully refreshed from Google Patents.
Patent US5537056A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5537056A Expired / Lapsed US ⏱️ 0.0 years remaining

Antifuse-based FPGA architecture without high-voltage isolation transistors

Assignee: Microsemi SoC Corp
•
Filing: 1994-09-30
•
Granted: 1996-07-16
•
Expires: 2014-09-30
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A programmable interface for selectively making connections between an output node of a logic module and an interconnection array in a field programmable gate array integrated circuit includes a first antifuse having a first electrode electrically connected to the output node and a second electrode connected to the first electrode of a second a second antifuse. The second electrode or the second antifuse is connected to the interconnection array. A high-voltage transistor, capable of withstanding programming voltages used in the integrated circuit to program the antifuses, is connected between the common connection comprising the second electrode of the first antifuse and the first electrode of the second antifuse and a fixed voltage potential such as ground. A control element of the high-voltage transistor is connected to circuitry for programming antifuses.

Inventors

  • 👤 John L. McCollum

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 04:48
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/1778; H03K19/17704

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 159 words
In a field programmable gate array integrated circuit including a plurality of logic modules and an interconnection array, a programmable interface for selectively making connections between an output node of a logic module and an interconnection node in said interconnection array, comprising: a first antifuse having a first electrode and a second electrode, said first electrode electrically connected to the output node; a second antifuse having a first electrode and a second electrode, said first electrode electrically connected to said second electrode of said first antifuse and said second electrode connected to the interconnection array; and a high-voltage transistor, capable of withstanding programming used in the integrated circuit to program the antifuses, connected between the common connection comprising said second electrode of said first antifuse and said first electrode of said second antifuse and a fixed voltage potential such as ground, said high-voltage transistor having a control element connected to circuitry for programming antifuses located on said integrated circuit.
Claim 2
Dependent Claim 159 words
In a field programmable gate array integrated circuit including a plurality of logic modules and an interconnection array, a programmable interface for selectively making connections between an output node of a logic module and an interconnection node in said interconnection array, comprising: a first antifuse having a first electrode and a second electrode, said first electrode electrically connected to the output node; a second antifuse having a first electrode and a second electrode, said first electrode electrically connected to said second electrode of said first antifuse and said second electrode connected to the interconnection array; and a high-voltage transistor, capable of withstanding programming used in the integrated circuit to program the antifuses, connected between the common connection comprising said second electrode of said first antifuse and said first electrode of said second antifuse and a fixed voltage potential such as ground, said high-voltage transistor having a control element connected to circuitry for programming antifuses located on said integrated circuit.
Claim 3
Dependent Claim 54 words
The programmable interface of claim 1, further including a programming-inhibit transistor connected between a common connection comprising said second electrode of said first antifuse and said first electrode of said second antifuse and a fixed voltage potential of about Vpp/2, said programming-inhibit transistor having a control element connected to said circuitry for programming antifuses.
Claim 4
Dependent Claim 54 words
The programmable interface of claim 1, further including a programming transistor connected between the common connection comprising said second electrode of said first antifuse and said first electrode of said second antifuse and a fixed voltage potential of about Vpp, said programming transistor having a control element connected to said circuitry for programming antifuses.
Claim 5
Dependent Claim 41 words
The programmable interface of claim 1, further including a first test transistor connected across said first antifuse and a second test transistor connected across said second antifuse, said first and second test transistors having control electrodes connected to test control circuitry.

References Cited (Backward Citations)

US4896296A Cited
US4855619A Cited
US4829203A Cited
US5045726A Cited
US5166557A Cited
US5095228A Cited
US5341030A Cited
US5428304A Cited
US5341043A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-07-16 2000-01-15 2000-07-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-07-16 2004-01-15 2004-07-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-07-16 2008-01-15 2008-07-16 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag