High resolution active matrix LCD cell design

Claim 2

A thin-film transistor panel used for active matrix display devices, comprising: a transparent insulative substrate; a plurality of islands of single crystal silicon formed on said insulative substrate and arranged in rows and columns; an NMOS transistor formed in each said island and having source, drain and channel regions, said source and drain regions of a first conductivity type, said transistor having a gate electrode at said channel region and source and drain electrodes, said transistor further having a pixel reference voltage region of a second conductivity type, said second conductivity type opposite said first conductivity type; a plurality of pixel electrodes spaced from said plurality of transistors with each pixel electrode connected to said drain electrode of a corresponding said first transistor; a plurality of control signal lines which are formed to extend in a direction of said rows and which connect to said gate electrodes of said transistors in said rows; a plurality of data signal lines which are formed to extend in a direction of said columns and which connect to said source electrodes of said transistors in said columns; a silicon body tie connection of a second conductivity type extending from said pixel reference voltage region to said channel region; and a first transparent metallization extending to each said first transistor and in contact with each said pixel reference voltage region, said first metallization forming a body tie buss.

Claim 3

Thin film transistor panel of claim 1 wherein said first metallization has a plurality of first areas, each said first area overlapping and spaced from each said corresponding pixel electrode by a dielectric, each said first area having a first size and said first size selected to achieve a first storage capacitor value.

Claim 4

Thin film transistor panel of claim 1 wherein an incident light on said transistor results in the generation of electron-hole pairs in said channel region and said silicon connection extracts said electron-hole pairs, thereby obviating the need for a separate light shield for said first transistors.

Claim 5

Thin film transistor panel of claim 1 wherein said first NMOS transistor has a snapback voltage of at least 10 volts.

Claim 6

Thin film transistor panel of claim 1 wherein said panel has an aperture ratio of at least 60 percent.

Claim 7

Thin film transistor panel of claim 1 further comprising integrated high mobility single crystal silicon transistors for use as row and column drivers.

Claim 8

A thin-film transistor panel used for active matrix display devices, comprising: a transparent insulative substrate; a first plurality of islands of single crystal silicon formed on said insulative substrate and arranged in rows and columns for a pixel switching function; a second plurality of islands of single crystal silicon formed at the periphery of said insulative substrate for the integrated row and column driver functions; an MOS transistor formed in each said first plurality island and having source, drain and channel regions, said source and drain regions of a first conductivity type, said transistor having a gate electrode at said channel region and source and drain electrodes, said transistor further having a pixel reference voltage region of a second conductivity type, said second conductivity type opposite said first conductivity type; a plurality of pixel electrodes spaced from said plurality of transistors with each pixel electrode connected to said drain electrode of a corresponding said first transistor; a plurality of control signal lines which are formed to extend in a direction of said rows and which connect to said gate electrodes of said transistors in said rows; a plurality of data signal lines which are formed to extend in a direction of said columns and which connect to said source electrodes of said transistors in said columns; a silicon body tie connection of a second conductivity type extending from said pixel reference voltage region to said channel region; and a first transparent metallization extending to each said first transistor and in contact with each said pixel reference voltage region, said first metallization forming a body tie buss.

Claim 9

A thin-film transistor panel used for active matrix display devices, comprising: a transparent insulative substrate; a first plurality of islands of single crystal silicon formed on said insulative substrate and arranged in rows and columns for a pixel switching function; a second plurality of islands of single crystal silicon formed at the periphery of said insulative substrate for the integrated row and column driver functions; an MOS transistor formed in each said first plurality island and having source, drain and channel regions, said source and drain regions of a first conductivity type, said transistor having a gate electrode at said channel region and source and drain electrodes, said transistor further having a pixel reference voltage region of a second conductivity type, said second conductivity type opposite said first conductivity type; a plurality of pixel electrodes spaced from said plurality of transistors with each pixel electrode connected to said drain electrode of a corresponding said first transistor; a plurality of control signal lines which are formed to extend in a direction of said rows and which connect to said gate electrodes of said transistors in said rows; a plurality of data signal lines which are formed to extend in a direction of said columns and which connect to said source electrodes of said transistors in said columns; a silicon body tie connection of a second conductivity type extending from said pixel reference voltage region to said channel region; and a first transparent metallization extending to each said first transistor and in contact with each said pixel reference voltage region, said first metallization forming a body tie buss.

Claim 10

Thin film transistor panel of claim 7 wherein said first metallization has a plurality of first areas, each said first area overlapping and spaced from each said corresponding pixel electrode by a dielectric, each said first area having a first size and said first size selected to achieve a first storage capacitor value.

Claim 11

Thin film transistor panel of claim 7 wherein an incident light on said transistor results in the generation of electron-hole pairs in said channel region and said silicon connection extracts said electron-hole pairs, thereby obviating the need for a separate light shield for said first transistors.

Claim 12

Thin film transistor panel of claim 7 wherein each pixel transistor is of NMOS type.

Claim 13

Thin film transistor of claim 10 wherein said first NMOS transistor has a snapback voltage of at least 10 volts.

Claim 14

Thin film transistor panel of claim 9 wherein each pixel transistor is of PMOS type.

Claim 15

Thin film transistor panel of claim 7 wherein said panel has an aperture ratio of at least 60 percent.

Claim 16

Thin film transistor panel of claim 7 wherein each of said second plurality of islands of single crystal silicon comprises both NMOS and PMOS transistors for CMOS integrated row and column driver functions.