Thin-film-transistor array with capacitance conductors

Claim 1

A thin-film-transistor (TFT) array for a display comprising: an array of TFTs arranged in rows and columns, each TFT having a gate, a source, and a drain; a plurality of spaced apart gate conductors, each gate conductor having opposed first and second ends, one of said gate conductors being provided for each row of said TFTs and connected to said gates of said TFTs in that row; a plurality of spaced apart source conductors crossing over said gate conductors, one of said source conductors being provided for each column of said TFT's and connected to said sources of said TFTs in that column; a matrix of pixel electrodes arranged in rows and columns corresponding to the rows and columns of said TFTs, said pixel electrodes in each of the rows being connected to said drains of corresponding TFTs in that row; a matrix of display sections arranged in rows and columns corresponding to the rows and columns of said TFTs, each of said display sections including a storage capacitor having first and second terminals with the first terminal connected to said drain of a corresponding TFT; and a plurality of storage capacitance conductors spaced from said gate conductors, said second terminals of said storage capacitors of said display section in each row being connected to corresponding storage capacitance conductors, the storage capacitance conductor connected through said storage capacitors to drains of TFTs for each row respectively being connected to the gate conductor connected to said gates of said TFTs in an adjacent row at at least one of said first and second ends of that gate conductor.