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US5535171A
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Data output buffer of a semiconducter memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-02-03
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Granted: 1996-07-09
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Expires: 2015-02-03
Abstract
Abstract A data output buffer of a semiconductor memory device using a clock having a fixed period from outside. The data output buffer has a data input part controlled and synchronized with a clock, for inputting data; a data latch device for latching data output through the data input part to thereby set up a predetermined delay time; a control signal input part controlled by the clock, for inputting a control signal; a latch controller for latching the control signal output through the control signal input part during a given time; a data output driver for receiving an output signal from the data latch device, the data output driver being controlled by the output signal of the latch controller; and an output device connected to the data output driver, for providing the data.
Inventors
- 👤 Chull-Soo Kim
- 👤 Hyun-Soon Jang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:40
CPC Classifications
H; H03; H03K; H03K19/00; G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C7/106; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356052; H03K3/35606
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
107 words
A semiconductor memory device operating in response to an external clock having a fixed period, comprising: a data latch which latches input data synchronized by said clock, said data latch outputting latched data; a latch controller which includes a control latch that latches a control signal in synchronization with said clock, said control latch outputting an output control signal; a data output driver which receives said latched data from said data latch and outputs said latched data as output data, said data output driver being controlled in accordance with said output control signal; and an output connected to said data output driver for outputting said output data.
Claim 2
Dependent Claim
107 words
A semiconductor memory device operating in response to an external clock having a fixed period, comprising: a data latch which latches input data synchronized by said clock, said data latch outputting latched data; a latch controller which includes a control latch that latches a control signal in synchronization with said clock, said control latch outputting an output control signal; a data output driver which receives said latched data from said data latch and outputs said latched data as output data, said data output driver being controlled in accordance with said output control signal; and an output connected to said data output driver for outputting said output data.
Claim 3
Dependent Claim
44 words
A semiconductor memory device according to claim 1, wherein said output control signal is synchronized with a clock pulse which precedes a data fetch clock pulse so that said output control signal is latched into said control latch prior to a data fetch operation.
Claim 4
Dependent Claim
48 words
A semiconductor memory device according to claim 1, wherein said latch controller includes a latch control transistor which has a latch control gate connected to said system clock so that said system clock synchronizes latching of said control signal through said latch control transistor to said control latch.
Claim 5
Dependent Claim
62 words
A semiconductor memory device according to claim 3, wherein said output control signal is latched into said latch control with a clock pulse which precedes a data fetch clock pulse and which is applied to said latch control gate of said latch control transistor so that said output control signal is latched into said control latch prior to a data fetch operation.
Claim 6
Dependent Claim
21 words
A semiconductor memory device according to claim 2 wherein said clock pulse also latches said input data into said data latch.
Claim 7
Dependent Claim
21 words
A semiconductor memory device according to claim 4 wherein said clock pulse also latches said input data into said data latch.
Claim 8
Dependent Claim
20 words
A semiconductor memory device according to claim 2, wherein said output control signal is a data output buffer enable signal.
Claim 9
Dependent Claim
29 words
A semiconductor memory device according to claim 1, wherein said latch controller is further controlled by a power up signal which maintains said control latch in an initial condition.
Claim 10
Dependent Claim
133 words
A data output buffer of a semiconductor memory device which operates in response to an external clock having a fixed period, comprising: a data input circuit which receives input data, said data input circuit outputting said input data as synchronized input data in synchronization with said clock; a data latch for latching said synchronized input data, said data latch outputting latch data; a latch controller which includes a control latch that latches a control signal in synchronization with said clock, said control latch outputting an output control signal; a data output driver which receives said latched data from said data latch, said data output driver controlling output of said latched data as output data using said output control signal; and an output connected to said data output driver for outputting said output data.
Claim 11
Dependent Claim
133 words
A data output buffer of a semiconductor memory device which operates in response to an external clock having a fixed period, comprising: a data input circuit which receives input data, said data input circuit outputting said input data as synchronized input data in synchronization with said clock; a data latch for latching said synchronized input data, said data latch outputting latch data; a latch controller which includes a control latch that latches a control signal in synchronization with said clock, said control latch outputting an output control signal; a data output driver which receives said latched data from said data latch, said data output driver controlling output of said latched data as output data using said output control signal; and an output connected to said data output driver for outputting said output data.
Claim 12
Dependent Claim
44 words
A data output buffer according to claim 9, wherein said output control signal is synchronized with a clock pulse which precedes a data fetch clock pulse so that said output control signal is latched into said control latch prior to a data fetch operation.
Claim 13
Dependent Claim
48 words
A data output buffer according to claim 9, wherein said latch controller includes a latch control transistor which has a latch control gate connected to said system clock so that said system clock synchronizes latching of said control signal through said latch control transistor to said control latch.
Claim 14
Dependent Claim
62 words
A data output buffer according to claim 11, wherein said output control signal is latched into said latch control with a clock pulse which precedes a data fetch clock pulse and which is applied to said latch control gate of said latch control transistor so that said output control signal is latched into said control latch prior to a data fetch operation.
Claim 15
Dependent Claim
21 words
A data output buffer according to claim 10 wherein said clock pulse also latches said input data into said data latch.
Claim 16
Dependent Claim
21 words
A data output buffer according to claim 12 wherein said clock pulse also latches said input data into said data latch.
Claim 17
Dependent Claim
20 words
A data output buffer according to claim 10, wherein said output control signal is a data output buffer enable signal.
Claim 18
Dependent Claim
29 words
A data output buffer according to claim 9, wherein said latch controller is further controlled by a power up signal which maintains said control latch in an initial condition.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-09 | 2000-01-08 | 2000-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-09 | 2004-01-08 | 2004-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-09 | 2008-01-08 | 2008-07-09 | $7700.00 | Window Closed / Lapsed |