US5430688A
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Synchronous dynamic random access memory
Assignee: Lapis Semiconductor Co Ltd
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Filing: 1994-06-06
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Granted: 1995-07-04
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Expires: 2014-06-06
Abstract
Abstract A synchronous dynamic random-access memory has transparent latch circuits that latch address signals in synchronization with a clock signal. An X-address is latched following activation of a first control signal; a Y-address is latched following activation of a second control signal. Data selected by the latched X- and Y-addresses are held in a data latch and output through a tri-state output circuit in synchronization with the clock signal. Data output starts a certain number of clock cycles from activation of the first control signal. The data can be output for one clock cycle, the same data can be output for two or more consecutive clock cycles, or different data can be output in consecutive clock cycles in an order determined by certain bits in the X- and Y-addresses.
Inventors
- 👤 Atsushi Takasugi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:46
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/408; G11C11/4082; G11C11/409; G11C11/4096
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
81 words
A synchronous dynamic random-access memory that provides data output in synchronization with a clock signal, comprising: a plurality of memory cells for storing data; an address signal output circuit for outputting address signals for selecting said memory cells, in synchronization with said clock signal; and a data output circuit for temporarily storing data stored in ones of said plurality of memory cells selected by said address signals, and consecutively outputting, in synchronization with said clock signal, the data thus temporarily stored.
Claim 2
Dependent Claim
81 words
A synchronous dynamic random-access memory that provides data output in synchronization with a clock signal, comprising: a plurality of memory cells for storing data; an address signal output circuit for outputting address signals for selecting said memory cells, in synchronization with said clock signal; and a data output circuit for temporarily storing data stored in ones of said plurality of memory cells selected by said address signals, and consecutively outputting, in synchronization with said clock signal, the data thus temporarily stored.
Claim 3
Dependent Claim
48 words
The synchronous dynamic random-access memory of claim 1, wherein said data output circuit comprises: a latch circuit having a plurality of bits for temporarily storing data of said memory cells; and an output control circuit for consecutively reading the data stored in the bits of said latch circuit.
Claim 4
Dependent Claim
30 words
The synchronous dynamic random-access memory of claim 2, wherein said output control circuit comprises a shift register for output of signals that consecutively select the bits in said latch circuit.
Claim 5
Independent Claim
82 words
A method of reading data from a synchronous dynamic random-access memory which has a plurality of memory cells for storing data and reads said data out at an output terminal in synchronization with a clock signal, comprising the steps of: selecting data, in synchronization with said clock signal, in a plurality of said memory cells; temporarily storing the data thus selected; and selectively transferring one bit of the data thus temporarily stored to said output terminal, in synchronization with said clock signal.
Claim 6
Independent Claim
82 words
A method of reading data from a synchronous dynamic random-access memory which has a plurality of memory cells for storing data and reads said data out at an output terminal in synchronization with a clock signal, comprising the steps of: selecting data, in synchronization with said clock signal, in a plurality of said memory cells; temporarily storing the data thus selected; and selectively transferring one bit of the data thus temporarily stored to said output terminal, in synchronization with said clock signal.
Claim 7
Dependent Claim
104 words
The method of reading according to claim 4, wherein the step of selectively transferring one bit of data thus temporarily stored comprises the further steps of: transferring a first bit of data which, among said data thus temporarily stored, was stored in a memory cell with a highest address; transferring a second bit of data which, among said data thus temporarily stored, was stored in a memory cell with a lowest address; and transferring a third bit of data which, among said data thus temporarily stored, was stored in a memory cell with an address intermediate between said highest address and said lowest address.
Claim 8
Dependent Claim
23 words
The method of reading according to claim 5, wherein said second bit is transferred after said first bit and before said third bit.
Claim 9
Dependent Claim
23 words
The method of reading according to claim 5, wherein said third bit is transferred after said first bit and before said second bit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-03 | 1999-01-02 | 1999-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-03 | 2003-01-02 | 2003-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-03 | 2007-01-02 | 2007-07-04 | $7700.00 | Window Closed / Lapsed |