Single chip adaptive filter utilizing updatable weighting techniques

Claim 2

An adaptive filtering system comprising: a multi-stage signal input tapped delay line including a plurality of storage modules operable for successively shifting discrete samples of an input signal along said delay line; a plurality of parallel multipliers respectively coupled to each of said storage modules, each of said multipliers operable for generating an output corresponding to the product of the discrete sample of said input signal received from a respective storage module and an updatable weighting coefficient; a summation circuit operable for providing an output signal corresponding to the sum of said products generated from said multipliers; and a weighting coefficient updating circuit operable for simultaneously providing to each of said multipliers distinct and synchronized updatable weighting coefficients as the sum of a predetermined weighting coefficient and an updating factor, said updating factor corresponding to a product of discrete samples of said input signal and discrete portions of an error signal determined as the difference between said output signal and a predetermined reference signal, wherein said updating circuit comprises a second multi-stage signal input tapped delay line including a second plurality of storage modules operable for successively shifting discrete samples of said input signal along said second delay line, and a second plurality of multipliers respectively coupled to each of said second plurality of storage modules, each of said second multipliers operable for generating an output corresponding to the product of the discrete sample of said input signal received from a respective second storage module and said discrete portions of said error signal.

Claim 3

The adaptive filter of claim 1, further comprising a differencing circuit coupled between said summation circuit and a reference signal source, said differencing circuit operable for calculating said error signal and providing it to said updating circuit.

Claim 4

The adaptive filter of claim 1, wherein said updating circuit comprises a second multi-stage signal input tapped delay line including a second plurality of storage modules operable for successively shifting discrete samples of said input signal along said second delay line.

Claim 5

The adaptive filter of claim 3 further comprising a delay circuit through which said input signal passes prior to being applied to said second delay line.

Claim 6

The adaptive filter of claim 3, wherein said updating circuit further comprises a second plurality of multipliers respectively coupled to each of said second plurality of storage modules, each of said second multipliers operable for generating an output corresponding to the product of the discrete sample of said input signal received from a respective second storage module and said discrete portions of said error signal.

Claim 7

The adaptive filter of claim 5, wherein said updating circuit further comprises a second summation circuit operable for providing an output signal corresponding to said updating factor.

Claim 8

The adaptive filter of claim 5, wherein said second delay line comprises a charge transfer device.

Claim 9

The adaptive filter of claim 7, wherein said charge transfer device comprises a charge coupled device shift register.

Claim 10

The adaptive filter of claim 1, wherein said delay line comprises a charge transfer device.

Claim 11

The adaptive filter of claim 9, wherein said charge transfer device comprises a charge coupled device shift register.

Claim 12

The adaptive filter of claim 10, wherein said discrete samples of said input signal comprise charge packets.

Claim 13

The adaptive filter of claim 11, wherein said storage modules comprise floating gate sensing electrodes, each of which are operable to provide a potential thereon corresponding to a charge packet.

Claim 14

The adaptive filter of claim 12, wherein said multipliers comprise analog-digital multipliers.

Claim 15

The adaptive filter of claim 13, wherein said multipliers comprise multiplying digital-to-analog converters.

Claim 16

The adaptive filter of claim 12, wherein said second multipliers comprise analog-digital multipliers.

Claim 17

The adaptive filter of claim 15, wherein said multipliers comprise multiplying digital-to-analog converters.

Claim 18

The adaptive filter of claim 1, wherein said input signal comprises an analog signal.

Claim 19

The adaptive filter of claim 1, wherein said input signal comprises a digital signal.

Claim 20

The adaptive filter of claim 1, wherein said delay line, said multipliers, said summation circuit, and said updating circuit are integrated on a single microprocessing chip.

Claim 21

The adaptive filter of claim 1 further comprising an iterative control unit operable for controlling said updating circuit to generate said updatable weighting coefficients at predetermined iterations.

Claim 22

The adaptive filter of claim 1, further comprising a differencing circuit coupled between said summation circuit and a reference signal source, said differencing circuit operable for calculating said error signal and providing it to said updating circuit.

Claim 23

The adaptive filter of claim 1, wherein said updating circuit comprises a second input signal delay line including a second plurality of storage modules operable for successively shifting discrete samples of said input signal along said second delay line.

Claim 24

The adaptive filter of claim 22 further comprising a delay circuit through which said input signal passes prior to being applied to said second delay line.

Claim 25

The adaptive filter of claim 22, wherein said updating circuit further comprises a second plurality of multipliers respectively coupled to each of said second plurality of storage modules, each of said second multipliers operable for generating an output corresponding to the product of the discrete sample of said input signal received from a respective second storage module and said discrete portions of said error signal.

Claim 26

The adaptive filter of claim 24, wherein said updating circuit further comprises a second summation circuit operable for providing an output signal corresponding to said updating factor.

Claim 27

The adaptive filter of claim 24, wherein said second delay line comprises a charge transfer device.

Claim 28

The adaptive filter of claim 26, wherein said charge transfer device comprises a charge coupled device shift register.

Claim 31

An adaptive filtering system comprising: an input signal delay line including a plurality of storage modules operable for successively shifting discrete samples of an input signal along said delay line; a plurality of parallel multipliers respectively coupled to each of said storage modules, each of said multipliers operable for generating an output corresponding to the product of the discrete sample of said input signal received from a respective storage module and a distinct updatable weighting coefficient; a summation circuit operable for providing an output signal corresponding to the sum of said products generated from said multipliers; and a weighting coefficient updating circuit including a plurality of parallel weighting coefficient updating circuit portions respectively coupled to each of said plurality of multipliers and operable for simultaneously providing to each of said multipliers said distinct updatable weighting coefficients, said distinct updatable weighting coefficients corresponding to a sum of a predetermined weighting coefficient and an updating factor, said updating factor corresponding to a product of discrete samples of said input signal and discrete portions of an error signal determined as the difference between said output signal and a predetermined reference signal, wherein said updating circuit comprises a second input signal delay line including a second plurality of storage modules operable for successively shifting discrete samples of said input signal along said second delay line, and a second plurality of multipliers respectively coupled to each of said second plurality of storage modules, each of said second multipliers operable for generating an output corresponding to the product of the discrete sample of said input signal received from a respective second storage module and said discrete portions of said error signal.

Claim 32

An adaptive filtering system comprising: an input signal delay line including a plurality of storage modules operable for successively shifting discrete samples of an input signal along said delay line; a plurality of parallel multipliers respectively coupled to each of said storage modules, each of said multipliers operable for generating an output corresponding to the product of the discrete sample of said input signal received from a respective storage module and a distinct updatable weighting coefficient; a summation circuit operable for providing an output signal corresponding to the sum of said products generated from said multipliers; and a weighting coefficient updating circuit including a plurality of parallel weighting coefficient updating circuit portions respectively coupled to each of said plurality of multipliers and operable for simultaneously providing to each of said multipliers said distinct updatable weighting coefficients, said distinct updatable weighting coefficients corresponding to a sum of a predetermined weighting coefficient and an updating factor, said updating factor corresponding to a product of discrete samples of said input signal and discrete portions of an error signal determined as the difference between said output signal and a predetermined reference signal, wherein said updating circuit comprises a second input signal delay line including a second plurality of storage modules operable for successively shifting discrete samples of said input signal along said second delay line, and a second plurality of multipliers respectively coupled to each of said second plurality of storage modules, each of said second multipliers operable for generating an output corresponding to the product of the discrete sample of said input signal received from a respective second storage module and said discrete portions of said error signal.

Claim 33

The adaptive filter of claim 29, wherein said delay line comprises a charge transfer device.

Claim 34

The adaptive filter of claim 30, wherein said charge transfer device comprises a charge coupled device shift register.

Claim 35

The adaptive filter of claim 31, wherein said discrete samples of said input signal comprise charge packets.

Claim 36

The adaptive filter of claim 32, wherein said storage modules comprise floating gate sensing electrodes, each of which are operable to provide a potential thereon corresponding to a charge packet.

Claim 37

The adaptive filter of claim 33, wherein said multipliers comprise analog-digital multipliers.

Claim 38

The adaptive filter of claim 34, wherein said multipliers comprise multiplying digital-to-analog converters.

Claim 39

The adaptive filter of claim 33, wherein said second multipliers comprise analog-digital multipliers.

Claim 40

The adaptive filter of claim 36, wherein said multipliers comprise multiplying digital-to-analog converters.

Claim 41

The adaptive filter of claim 29, wherein said input signal comprises an analog signal.

Claim 42

The adaptive filter of claim 29, wherein said input signal comprises a digital signal.

Claim 43

The adaptive filter of claim 29, wherein said delay line, said multipliers, said summation circuit, and said updating circuit are integrated on a single microprocessing chip.