Abstract A pipelined charge coupled analog to digital converter which provides a plurality of serially arranged pipelined stages that are connected to pass signal and reference charge packets from stage to stage in a serial progression. The pipelined analog to digital converter includes one stage for each bit desired in the output bit stream, and thus, an analog to digital converter providing an n bit digital word corresponding to the input analog signal charge, includes n stages. While the time necessary to perform the analog to digital conversion is the sum of operating times of all the stages, because the converter is pipelined, each successive n bit digital word representing a different successive charge packet is produced succeeding a preceding digital word representing a preceding signal charge packet, by a delay equal to the processing time of only a single stage. Thus, a charge coupled A/D system is provided including a plurality of pipelined stages for performing successive approximations on a reference charge Q r and an input analog signal charge Q s wherein said pipelined stages include charge processing means each coupled only to directly adjacent stages for performing an inequality function to provide a bit string b 1 through b n representing a digital representation of said input analog signal charge Q s .
A charge coupled A/D system including a plurality of pipelined charge processing stages for performing successive approximations on a reference analog charge Q r and an input signal charge Q s wherein: each of said pipelined charge processing stages are coupled only to directly adjacent stages for propagation of reference and input signal charges, each said pipelined charge processing stage includes charge processing means, including comparator means, for performing an inequality function, said plurality of pipelined charge processing stages providing a bit string b 1 through b N representing a digital representation of said input analog signal charge Q s ; which includes a different stage for each bit, b 1 through b N , of said digital representation an in which each stage, other than an initial and final stage comprise: charge splitter means subjected to an input charge packet Qi for delivering, on separate charge transfer paths, a pair of charge packets Qi/2; a pair of commonly controlled charge switching means, each with a charge input and a pair of outputs, each said charge switching means connected to receive a one of said charge packets Qi/2; a single electrode and means coupling an output of each of said charge switching means to said electrode; and a pair of field gate means for generating input voltages for said comparator means each coupled to other outputs of said charge switching means; and means for controlling said charge switching means whereby a charge packet Qi/2 is input to one or another of said field gate means regardless of a condition of said charge switching means.
Claim 2
Dependent Claim
264 words
A charge coupled A/D system including a plurality of pipelined charge processing stages for performing successive approximations on a reference analog charge Q r and an input signal charge Q s wherein: each of said pipelined charge processing stages are coupled only to directly adjacent stages for propagation of reference and input signal charges, each said pipelined charge processing stage includes charge processing means, including comparator means, for performing an inequality function, said plurality of pipelined charge processing stages providing a bit string b 1 through b N representing a digital representation of said input analog signal charge Q s ; which includes a different stage for each bit, b 1 through b N , of said digital representation an in which each stage, other than an initial and final stage comprise: charge splitter means subjected to an input charge packet Qi for delivering, on separate charge transfer paths, a pair of charge packets Qi/2; a pair of commonly controlled charge switching means, each with a charge input and a pair of outputs, each said charge switching means connected to receive a one of said charge packets Qi/2; a single electrode and means coupling an output of each of said charge switching means to said electrode; and a pair of field gate means for generating input voltages for said comparator means each coupled to other outputs of said charge switching means; and means for controlling said charge switching means whereby a charge packet Qi/2 is input to one or another of said field gate means regardless of a condition of said charge switching means.
Claim 3
Dependent Claim
27 words
The apparatus of claim 1 in which said means for controlling said charge switching means includes an output from a comparator means of a directly preceding stage.
Claim 4
Dependent Claim
22 words
The system of claim 1 which further includes a deskewing register with at least one stage in each of said pipelined stages.