Analog to digital conversion by charge transfer device

Claim 1

An analog to digital converter employing a charge transfer matrix comprising: a semiconductor substrata for storage of charge regions representing the analog signal and other comparison signals; a plurality of electrodes cooperatively positioned in four linear channels of 2N - 1 cells, where N is the number of digital bits required in the digital answer, individual cells being defined by the physical extend of the associated electrode and being numbered from one commencing with the input cell; a first one of said electrode channels includes electrodes shaped to provide only full charge transfer cells to provide a channel for storage and transfer of the analog signal and for addition of signal thereto; a second one of said electrode channels arranged adjacent said first electrode channel including odd-numbered full charge transfer cells and alternate even-numbered charge division cells whereby the initial charge placed therein is reduced to successively approximate the charge in said first channel upon sequented charge transfer; a third one of said four electrode channels positioned on the opposite side of said second electrode channel from said first electrode channel and including alternate, oddnumbered full charge transfer cells and even-numbered charge division cells for establishing a comparison voltage channel; a fourth one of said four electrode channels positioned on the opposite side of said third electrode channel from said second electrode channel and including alternate odd-numbered full charge transfer cells and even-numbered charge division cells for cooperation with said third one of said four electrode channels; a first series of charge transfer gates extending between and for moving charges between odd and even numbered cells in each channel; a second series of charge transfer gates arranged to extend between one of each pair of said charge division cells in said second one of said electrode channels and an adjacent, evennumbered full charge transfer cell in said first one of said electrode channels for charge transfer therebetween whereby a charge from said charge division cells may be added to the charge within said analog signal channel; a third series of charge transfer gates arranged to extend between one of each pair of said even-numbered charge division cells in said third electrode channel and one of each pair of even-numbered charge division cElls in said fourth electrode channel for charge transfer therebetween for charge transfer and addition therebetween; a fourth series of charge transfer gates arranged to extend between each of said even-numbered and said odd-numbered cells in said first electrode channel and between each of the other even-numbered charge division cells in said second, third, and fourth electrode channels and the odd-numbered cells therein for charge transfer therebetween; a fifth series of charge transfer gates arranged to extend between said one of each pair of said even-numbered charge division cells and said odd-numbered full charge transfer cells in said third electrode channel for charge transfer therebetween; logic controlled clocking circuit means connected to each of the aforerecited charge transfer gates for effecting a timely migration of electrical charges between the associated cells in dependence on the charge potential therebetween; and differential amplifier means connected between the odd-numbered full charge transfer cells in said first electrode channel and the odd-numbered full charge transfer cells in said fourth electrode channel for producing an output when a predetermined difference exists therebetween whereby a digital word output results in dependence upon the particular charge migrations established by the said first through fifth series of charge transfer gates and logic controlled clocking circuit means as the charge in the fourth electrode channel is processed to approximate the analog signal input of the first electrode channel.