Echo canceler with cascaded filter structure

Claim 2

An echo canceler for canceling an echo as a leakage component to a four-wire receiving end in a two-wire/four-wire conversion hybrid circuit when a transmitted signal is sent from a four-wire line to a two-wire line, comprising: transmitting means for receiving a transmitted binary data sequence having a predetermined interval therebetween, converting the transmitted binary data sequence to a given coded signal including sign designation signals, and producing the given coded signal and sign designation signals at an output; an adaptive digital filter including a plurality of delay elements for receiving the transmitted binary data sequence, delaying the transmitted binary data sequence by one sampling interval so as to obtain delayed data sequences, and dividing the delayed data sequences into a plurality of groups of signal components, the groups of signal components being produced as address signals, respectively, and a plurality of memories respectively having memory cells the storage contents of which are read out in response to the address signals from said delay elements and sign designation signals such that a first memory among said plurality of memories directly receives the sign designation signal, and 2nd through Nth (n is 2, 3, 4, . . . ) memories among said plurality of memories respectively receive the sign designation signals through delay lines so that the Nth memory receives the sign designation signal delayed by a time interval corresponding to delay time of an (N-1)th delay element among said plurality of delay elements, the number of said memories being equal to that of the plurality of groups of signal components; a timing signal generator for generating additional address signals to said plurality of memories; a plurality of D/A converters for converting readout digital signals from said plurality of memories to analog signals, respectively; an analog adder for adding all the analog signals from said plurality of D/A converters to produce an echo replica; a hybrid circuit for receiving the coded signal from said transmitting means, and a received signal, including additive noise, from said two-wire line, the coded signal being repreduced as said echo signal; a low-pass filter for receiving the echo signal, the received signal including the additive noise and for eliminating a high frequency signal component therefrom; a subtractor for receiving a filtered signal from said low-pass filter and the echo replica from said analog adder and for subtracting the echo replica from the filtered signal so as to produce an error signal; a sample-and-hold circuit for receiving said error signal and for producing a sampled signal; an A/D converter for receiving the sampled signal from said sample-and-hold circuit and for producing a digital signal; and receiving means for receiving and decoding the sampled signal and for sending a decoded signal therefrom, said adaptive digital filter further including a plurality of 2-input adders, each of which receives a signal from said A/D converter and one of the digital signals read out from said plurality of memories, the number of said 2-input adders being equal to that of said memories, and sum signals from said 2-input adders being stored in said memories, respectively.

Claim 3

An echo canceler according to claim 1, wherein said adaptive digital filter further includes: a scaling circuit for processing the digital signal from said A/D converter in accordance with predetermined scaling.

Claim 4

An echo canceler for canceling an echo as a leakage component to a four-wire receiving end in a two-wire/four-wire conversion hybrid circuit when a transmitted signal is sent from a four-wire line to a two-wire line, comprising: a plurality of adaptive digital filters, each of which comprises: a plurality of delay elements for receiving a transmitted binary data sequence, delaying the transmitted binary data sequence by one sampling interval so as to obtain delayed data sequences, and dividing the delayed data sequences into a plurality of groups of signal components, the groups of signal components being produced as address signals, respectively, a plurality of memories respectively having memory cells the storage contents of which are read out in response to the address signals, the number of said memories being equal that that of the plurality of groups of signal components, a scaling circuit for performing predetermined scaling, and a plurality of 2-input adders, each of which receives a scaled signal from said scaling circuit and one of the digital signals read out from said plurality of memories, the number of said 2-input adders being equal to that of said memories, and sum signals from said 2-input adders being stored in said memories, respectively; a plurality of switching means respectively connected to said plurality of adaptive digital filters so as to sequentially cause said plurality of adaptive digital filters to perform a convergence operation; a timing generator for supplying a control signal to said plurality of switching means, so that a first adaptive digital filter among said plurality of adaptive digital filters partially cancels the echo, and an ith (i=2, 3, . . . ) adaptive digital filter cancels a residual echo which is left uncanceled by the first to (i-1)th adaptive digital filters; and a pluraity of D/A converters respectively corresponding to said memories so as to sequentially receive and convert the readout digital signals to analog signals.

Claim 5

An echo canceler for canceling an echo as a leakage component to a four-wire receiving end in a two-wire/four-wire conversion hybrid circuit when a transmitted signal is sent from a four-wire line to a two-wire line, comprising: a plurality of adaptive digital filters, each of which comprises: a plurality of delay elements for receiving a transmitted binary data sequence, delaying the transmitted binary data sequence by one sampling interval so as to obtain delayed data sequences, and dividing the delayed data sequences into a plurality of groups of signal components, the groups of signal components being produced as address signals, respectively, a plurality of memories respectively having memory cells the storage contents of which are read out in response to the address signals, the number of said memories being equal that that of the plurality of groups of signal components, a scaling circuit for performing predetermined scaling, and a plurality of 2-input adders, each of which receives a scaled signal from said scaling circuit and one of the digital signals read out from said plurality of memories, the number of said 2-input adders being equal to that of said memories, and sum signals from said 2-input adders being stored in said memories, respectively; a plurality of switching means respectively connected to said plurality of adaptive digital filters so as to sequentially cause said plurality of adaptive digital filters to perform a convergence operation; a timing generator for supplying a control signal to said plurality of switching means, so that a first adaptive digital filter among said plurality of adaptive digital filters partially cancels the echo, and an ith (i=2, 3, . . . ) adaptive digital filter cancels a residual echo which is left uncanceled by the first to (i-1)th adaptive digital filters; and a pluraity of D/A converters respectively corresponding to said memories so as to sequentially receive and convert the readout digital signals to analog signals.

Claim 6

An echo canceler according to claim 3, further including: transmitting means for receiving the transmitted binary data sequence, converting the transmitted binary data sequence to a given coded signal, and producing the given coded signal at an output; an analog adder for adding all the analog signals from said plurality of D/A converters to produce an echo replica; a hybrid circuit for receiving the coded signal from said transmitting means, and a received signal, including additive noise, from said two-wire line, the coded signal being reproduced as said echo signal; a low-pass filter for receiving the echo signal, the received signal including the additive noise and for eliminating a high frequency signal component therefrom; a subtractor for receiving a filtered signal from said low-pass filter and the echo replica from said analog adder and for subtracting the echo replica from the filtered signal so as to produce an error signal; a sample-and-hold circuit for receiving the error signal and for producing a sampled signal; an A/D converter for receiving the sampled signal from said sample-and-hold circuit and for producing a digital signal to be supplied to said scaling circuit; and receiving means for receiving and decoding the sampled signal and for sending a decoded signal therefrom.

Claim 7

An echo canceler according to claims 3 or 4, wherein said timing generator comprises a control signal generator for receiving the error replica from said analog adder, and the error signal from said subtractor and for generating a control signal to said plurality of switching means.

Claim 8

An echo canceler for canceling an echo as a leakage component to a four-wire receiving end in a two-wire/four-wire conversion hybrid circuit when a transmitted signal is sent from a four-wire line to a two-wire line, comprising: a plurality of adaptive digital filters including a first adaptive digital filter and a second adaptive filter operable to perform a two-step convergence operation, said first adaptive digital filter having a plurality of delay elements, each of which receives a transmitted signal such that a first delay element among said pluraity of delay elements receives the transmitted signal, and an ith (i=2, 3, 4, . . . ) delay element thereamong receives the transmitted signal delayed by a predetermined time interval from an (i-1)th delay element thereamong, a pluraity of coefficient signal generating means, each of which receives an error signal and the transmitted signal such that the first coefficient signal generating means among said plurality of coefficient signal generating means directly receives the transmitted signal and ith (i=2, 3, 4, . . . ) coefficient signal generating means thereamong receives the delayed signal from said (i-1) delay element, said plurality of coefficient signal generating means respectively producing predetermined coefficient signals in accordance with the corresponding transmitted signal and the error signal, a plurality of multipliers, each of which receives a corresponding one of the coefficient signals and the transmitted signal such that a first multiplier among said pluraity of multipliers directly receives the transmitted signal and an ith multiplier thereamong receives the delayed transmitted signal from said (i-1)th delay element, and a first adder for adding outputs from said plurality of multipliers so as to produce an echo replica, and said second adaptive digital filter having a plurality of delay elements for receiving the transmitted binary data sequence, delaying the transmitted binary data sequence by one sampling interval so as to obtain a delayed data sequence, and dividing the delayed data sequence into a plurality of groups of signal components, the groups of signal components being supplied as address signals, respectively, a plurality of memories respectively having memory cells the storage contents of which are read out in response to the address signals, the number of said memories being equal to that of the plurality of groups of signal components, a scaling circuit for performing predetermined scaling, and a plurality of 2-input adders, each of which receives a scaled signal from said scaling circuit and one of the readout digital signals from said plurality of memories, the number of said 2-input adders being equal to that of said memories, and sum signals from said 2-input adders being stored in said memories, respectively; a plurality of D/A converters, said first adaptive digital filter coupled to a single D/A converter among said plurality of D/A converters, and said second adaptive digital filter coupled to said D/A converters which number the same as said memories; a plurality of subtractors respectively corresponding to said plurality of adaptive digital filters, an output from said single D/A converter being directly supplied to a corresponding subtractor among said plurality of subtractors; and at least one second adder corresponding to said second adaptive digital filter; a plurality of switching means respectively connected to said plurality of adaptive digital filters so as to sequentially cause said plurality of adaptive digital filters to perform said convergence operation; and a timing generator for supplying a control signal to said plurality of switching means, so that a first adaptive digital filter among said pluraity of adaptive digital filters partially cancels the echo, and an ith (i=2, 3, . . . ) adaptive digital filter thereamong cancels a residual echo which is left uncanceled by the first to (i-1) the adaptive digital filters.

Claim 9

An echo canceler for canceling an echo as a leakage component to a four-wire receiving end in a two-wire/four-wire conversion hybrid circuit when a transmitted signal is sent from a four-wire line to a two-wire line, comprising: a plurality of adaptive digital filters including a first adaptive digital filter and a second adaptive filter operable to perform a two-step convergence operation, said first adaptive digital filter having a plurality of delay elements, each of which receives a transmitted signal such that a first delay element among said pluraity of delay elements receives the transmitted signal, and an ith (i=2, 3, 4, . . . ) delay element thereamong receives the transmitted signal delayed by a predetermined time interval from an (i-1)th delay element thereamong, a pluraity of coefficient signal generating means, each of which receives an error signal and the transmitted signal such that the first coefficient signal generating means among said plurality of coefficient signal generating means directly receives the transmitted signal and ith (i=2, 3, 4, . . . ) coefficient signal generating means thereamong receives the delayed signal from said (i-1) delay element, said plurality of coefficient signal generating means respectively producing predetermined coefficient signals in accordance with the corresponding transmitted signal and the error signal, a plurality of multipliers, each of which receives a corresponding one of the coefficient signals and the transmitted signal such that a first multiplier among said pluraity of multipliers directly receives the transmitted signal and an ith multiplier thereamong receives the delayed transmitted signal from said (i-1)th delay element, and a first adder for adding outputs from said plurality of multipliers so as to produce an echo replica, and said second adaptive digital filter having a plurality of delay elements for receiving the transmitted binary data sequence, delaying the transmitted binary data sequence by one sampling interval so as to obtain a delayed data sequence, and dividing the delayed data sequence into a plurality of groups of signal components, the groups of signal components being supplied as address signals, respectively, a plurality of memories respectively having memory cells the storage contents of which are read out in response to the address signals, the number of said memories being equal to that of the plurality of groups of signal components, a scaling circuit for performing predetermined scaling, and a plurality of 2-input adders, each of which receives a scaled signal from said scaling circuit and one of the readout digital signals from said plurality of memories, the number of said 2-input adders being equal to that of said memories, and sum signals from said 2-input adders being stored in said memories, respectively; a plurality of D/A converters, said first adaptive digital filter coupled to a single D/A converter among said plurality of D/A converters, and said second adaptive digital filter coupled to said D/A converters which number the same as said memories; a plurality of subtractors respectively corresponding to said plurality of adaptive digital filters, an output from said single D/A converter being directly supplied to a corresponding subtractor among said plurality of subtractors; and at least one second adder corresponding to said second adaptive digital filter; a plurality of switching means respectively connected to said plurality of adaptive digital filters so as to sequentially cause said plurality of adaptive digital filters to perform said convergence operation; and a timing generator for supplying a control signal to said plurality of switching means, so that a first adaptive digital filter among said pluraity of adaptive digital filters partially cancels the echo, and an ith (i=2, 3, . . . ) adaptive digital filter thereamong cancels a residual echo which is left uncanceled by the first to (i-1) the adaptive digital filters.

Claim 10

An echo canceler according to claim 6 further comprising: transmitting means for receiving the transmitted binary data sequence, converting the transmitted binary data sequence to a given coded signal, and producing the given coded signal at an output; a hybrid circuit for receiving the coded signal from said transmitting means, and a received signal, including additive noise, from said two-wire line, the coded signal being reproduced as said echo signal; a low-pass filter for receiving the echo signal, the received signal including the additive noise and for eliminating a high frequency signal component; an A/D converter for receiving the sampled signal from said sample-and-hold circuit and for producing a digital signal to be supplied to said scaling circuit; and receiving means for receiving and decoding the sampled signal and for sending a decoded signal therefrom.