Fast multiplierless architecture for general purpose VLSI FIR digital filters with minimized hardware

Claim 1

A multiplierless digital transversal filter comprising: a first set of N registers for respectfully receiving and storing respective coefficients of a set of N filter tap coefficients C i , where i=0, 1, . . . N-1, each coefficient having L bits in successive bit positions j, where j=0, 1, . . . , L-1; means for receiving successive samples x n of a digital input word X, all bits of a sample x n being received in parallel and each such sample having M bits in successive bit positions k, where k=0, 1, . . . , M-1; means to bit slice each input word sample x n into a plurality of segments, each segment having a number w of bits, each segment constituting a processing plane of said filter; means to perform a convolution of the w-bits of the bit-slice segment of each of said processing planes by said set of coefficients C i in parallel, each segment being convolved with said set of coefficients C i , the output of each processing plane being the convolution of the w-bits of the bit slice segment thereof and the L bits of each of said set of coefficients C i ; means to add the results of all said convolutions of all of said M bits of each input word sample x n , the sum so derived being Y n ; means to output said sum Y n as a filtered digital output signal sample corresponding to said input word sample x n ; and means for biasing the input word samples x n and the coefficients C i so that they represent only positive numbers, whereby said sum Y n is derived over all four possible quadrants of the results of each of said convolutions.