US4745570A
Expired / Lapsed
US
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Binary multibit multiplier
Assignee: International Business Machines Corp
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Filing: 1986-05-27
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Granted: 1988-05-17
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Expires: 2006-05-27
Abstract
Abstract A digital multiplier has recoders for recoding the multiplier bits to form selection bits which are applied to selectors for selecting forms of the multiplicand, either the multiplicand itself or multiples of the multiplicand, the selected forms being applied to adders which produce partial products, the adders being interconnected to produce the product. Special product generators simultaneously generate multiples of the multiplicand which are applied to the selectors.
Inventors
- 👤 Richard A. Diedrich
- 👤 Jay A. Lawrence
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:20
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/533; G06F7/5334; G06F7/5336
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
135 words
A digital multiplier circuit for generating a product from multi bit inputs representing a multi bit multiplicand and a multi bit multiplier comprising: a plurality of special product generators having inputs for receiving predetermined bits of the multiplicand to generate therefrom outputs which are multiples of said multiplicand together with sign bits for said multiples of said multiplicand, a plurality of recoders for recoding at least more than two bits of said multiplier to generate selection signals for selecting different multiples of the multiplicand including the multiplicand itself, a plurality of selectors each connected to receive multiples of the multiplicand including the multiplicand itself and connected to receive said selection signals from said recoders; and, a plurality of adders connected to said selectors and the outputs of said adders being interconnected to generate the product.
Claim 2
Dependent Claim
135 words
A digital multiplier circuit for generating a product from multi bit inputs representing a multi bit multiplicand and a multi bit multiplier comprising: a plurality of special product generators having inputs for receiving predetermined bits of the multiplicand to generate therefrom outputs which are multiples of said multiplicand together with sign bits for said multiples of said multiplicand, a plurality of recoders for recoding at least more than two bits of said multiplier to generate selection signals for selecting different multiples of the multiplicand including the multiplicand itself, a plurality of selectors each connected to receive multiples of the multiplicand including the multiplicand itself and connected to receive said selection signals from said recoders; and, a plurality of adders connected to said selectors and the outputs of said adders being interconnected to generate the product.
Claim 3
Dependent Claim
19 words
The digital multiplier of claim 1 wherein said plurality of special products generators generate multiples of said multiplicand simultaneously.
Claim 4
Dependent Claim
22 words
The digital multiplier of claim 1 wherein said multiplicand and said multiplier are each sixteen bits and said product is thirty-two bits.
Claim 5
Dependent Claim
91 words
The digital multiplier of claim 1 wherein said adders are interconnected in a manner that a first adder of the plurality of adders has at least a portion of its output connected to the input of another adder of said plurality of adders, and the last adder of said plurality of adders has its input connected to at least a portion of the output of a preceding adder and its output is at least a portion of the output of said multiplier to provide at least a portion of the product.
Claim 6
Dependent Claim
18 words
The digital multiplier of claim 1 wherein said selectors have the same number of bits as said adders.
Claim 7
Dependent Claim
63 words
The digital multiplier of claim 1 wherein each bit position of said selectors consists of a plurality of logical AND circuits corresponding in number to the number of selection signals from one of said recoders, each logical AND circuit having an input to receive a predetermined form of the multiplicand and an input for receiving one of the selection signals from said recoders.
Claim 8
Dependent Claim
16 words
The digital multiplier of claim 1 wherein each of said recoders consists of identical logic elements.
Claim 9
Dependent Claim
142 words
The digital multiplier of claim 7 wherein each recoder has five inputs, the first input of the first recoder of said plurality of recoders is to receive a forced logical zero and the other inputs are connected to receive predetermined multiplier bits, the multiplier bit applied to the fifth input of said first recoder also being applied to the first input of the second recoder which has its other inputs connected to predetermined multiplier bits, the predetermined multiplier bit applied to the fifth input of the second recoder also being applied to the first input of the third recoder which has its other inputs connected to predetermined multiplier bits, the multiplier bit applied to the fifth input of said third recoder being also applied to the first input of the fourth recoder which has its other inputs connected to predetermined multiplier bits.
Claim 10
Dependent Claim
21 words
The digital multiplier of claim 8 wherein each recoder generates from said inputs eight selection signals and a negative control signal.
Claim 11
Dependent Claim
14 words
The digital multiplier of claim 1 wherein said plurality of recoders comprise four recoders.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-17 | 1991-11-16 | 1992-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-17 | 1995-11-16 | 1996-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-17 | 1999-11-16 | 2000-05-17 | $7700.00 | Window Closed / Lapsed |