Patent US5534821A successfully refreshed from Google Patents.
US5534821A
Expired / Lapsed
US
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Charge pump circuits for PLL frequency synthesizer
Assignee: FIJITSU VLSI Ltd
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Filing: 1994-08-11
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Granted: 1996-07-09
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Expires: 2014-08-11
Abstract
Abstract A PLL frequency synthesizer, which comprises a voltage controlled oscillator, and a comparison frequency divider for dividing a frequency of the output signal from the voltage controlled oscillator to output a comparison signal. A phase comparator in the synthesizer compares a phase of a reference signal to be fed thereto with a phase of the comparison signal, and generates first and second phase difference signals, based on the compared result. The synthesizer further includes a charge-pump circuit operated based on the first and second phase difference signals, and having an output terminal connected to the voltage controlled oscillator. The charge-pump circuit includes a first bipolar transistor connected between a high-potential power supply and the output terminal, and a second bipolar transistor connected between a low-potential power supply and the output terminal. The first and second bipolar transistors are controlled based on the first and second phase difference signals, respectively. At least one of the first and second bipolar transistors is an emitter-follower type. In another embodiment, a node is provided between two switches formed by CMOS transistors, to serve as an output terminal of the charge-pump circuit. In a further embodiment, two PMOS transistors are provided as switches, and a node is provided therebetween to serve as an output terminal of the charge-pump circuit.
Inventors
- 👤 Takehiro Akiyama
- 👤 Katsuya Shimomura
- 👤 Kouzi Takekawa
- 👤 Takehito Doi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:23
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/66; H03K17/665; H03K17/666; H03K17/667; H03K17/687; H03K17/6871; H03K17/6872; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891; H03L7/0895; H03L7/0896
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
248 words
A PLL frequency synthesizer circuit comprising: a voltage controlled oscillator for generating an output signal having a variable frequency; a comparison frequency divider for dividing a frequency of said output signal from said voltage controlled oscillator to output a comparison signal; a phase comparator for comparing a phase of a reference signal to be fed thereto with a phase of said comparison signal and for generating a first phase difference signal and a second phase difference signal based on the compared result; and a charge-pump circuit to be operated based on said first and second phase difference signals and having an output terminal for outputting a voltage signal, said output terminal being connected to said voltage controlled oscillator, the frequency of said output signal being influenced by the voltage signal, wherein said charge-pump circuit includes: a first bipolar transistor, connected between a high-potential power supply and said output terminal, to be controlled based on said first phase difference signal; a second bipolar transistor, connected between a low-potential power supply and said output terminal, to be controlled based on said second phase difference signal; and both of said first and second bipolar transistors being emitter-follower types; wherein said first bipolar transistor is an NPN transistor having a collector connected to said high-potential power supply and an emitter connected to said output terminal; and wherein said second bipolar transistor is a PNP transistor having a collector connected to said low-potential power supply and an emitter connected to said output terminal.
Claim 2
Dependent Claim
248 words
A PLL frequency synthesizer circuit comprising: a voltage controlled oscillator for generating an output signal having a variable frequency; a comparison frequency divider for dividing a frequency of said output signal from said voltage controlled oscillator to output a comparison signal; a phase comparator for comparing a phase of a reference signal to be fed thereto with a phase of said comparison signal and for generating a first phase difference signal and a second phase difference signal based on the compared result; and a charge-pump circuit to be operated based on said first and second phase difference signals and having an output terminal for outputting a voltage signal, said output terminal being connected to said voltage controlled oscillator, the frequency of said output signal being influenced by the voltage signal, wherein said charge-pump circuit includes: a first bipolar transistor, connected between a high-potential power supply and said output terminal, to be controlled based on said first phase difference signal; a second bipolar transistor, connected between a low-potential power supply and said output terminal, to be controlled based on said second phase difference signal; and both of said first and second bipolar transistors being emitter-follower types; wherein said first bipolar transistor is an NPN transistor having a collector connected to said high-potential power supply and an emitter connected to said output terminal; and wherein said second bipolar transistor is a PNP transistor having a collector connected to said low-potential power supply and an emitter connected to said output terminal.
Claim 3
Dependent Claim
32 words
The PLL frequency synthesizer circuit according to claim 1 further comprising a reference counter for dividing a reference frequency of an oscillation signal having a predetermined frequency to generate said reference signal.
Claim 4
Dependent Claim
35 words
The PLL frequency synthesizer circuit according to claim 1 further comprising a low-pass filter, provided between said charge-pump circuit and said voltage controlled oscillator, for smoothing said voltage signal to generate a control voltage signal.
Claim 5
Dependent Claim
150 words
A charge-pump circuit for use in a PLL frequency synthesizer circuit, the charge-pump circuit being operated based on first and second phase difference signals to be fed thereto, comprising: an output terminal for outputting a voltage signal; a first bipolar transistor, connected between a high-potential power supply and said output terminal, to be controlled based on the first phase difference signal; a second bipolar transistor, connected between a low-potential power supply and said output terminal, to be controlled based on the second phase difference signal; and both of said first and second bipolar transistors being emitter-follower types; wherein said first bipolar transistor is an NPN transistor having a collector connected to said high-potential power supply and an emitter connected to said output terminal; and wherein said second bipolar transistor is a PNP transistor having a collector connected to said low-potential power supply and an emitter connected to said output terminal.
Claim 6
Dependent Claim
150 words
A charge-pump circuit for use in a PLL frequency synthesizer circuit, the charge-pump circuit being operated based on first and second phase difference signals to be fed thereto, comprising: an output terminal for outputting a voltage signal; a first bipolar transistor, connected between a high-potential power supply and said output terminal, to be controlled based on the first phase difference signal; a second bipolar transistor, connected between a low-potential power supply and said output terminal, to be controlled based on the second phase difference signal; and both of said first and second bipolar transistors being emitter-follower types; wherein said first bipolar transistor is an NPN transistor having a collector connected to said high-potential power supply and an emitter connected to said output terminal; and wherein said second bipolar transistor is a PNP transistor having a collector connected to said low-potential power supply and an emitter connected to said output terminal.
Claim 7
Dependent Claim
224 words
A PLL frequency synthesizer circuit comprising: a voltage controlled oscillator for generating an output signal having a variable frequency; a comparison frequency divider for dividing a frequency of said output signal from said voltage controlled oscillator to output a comparison signal; a phase comparator for comparing a phase of a reference signal to be fed thereto with a phase of said comparison signal, and for generating a first phase difference signal and a second phase difference signal based on the compared result; and a charge-pump circuit to be operated based on said first and second phase difference signals and having an output terminal for outputting a voltage signal, said output terminal being connected to said voltage controlled oscillator, the frequency of said output signal being influenced by said voltage signal, wherein said charge-pump circuit includes: a first analog switch connected between a high-potential power supply and said output terminal, said first analog switch being controlled based on said first phase difference signal, said first analog switch being composed of a pair of PMOS and NMOS transistors connected in parallel; and a second analog switch connected between said output terminal and a low-potential power supply, said second analog switch being controlled based on said second phase difference signal., said second analog switch being composed of a pair of PMOS and NMOS transistors connected in parallel.
Claim 8
Dependent Claim
224 words
A PLL frequency synthesizer circuit comprising: a voltage controlled oscillator for generating an output signal having a variable frequency; a comparison frequency divider for dividing a frequency of said output signal from said voltage controlled oscillator to output a comparison signal; a phase comparator for comparing a phase of a reference signal to be fed thereto with a phase of said comparison signal, and for generating a first phase difference signal and a second phase difference signal based on the compared result; and a charge-pump circuit to be operated based on said first and second phase difference signals and having an output terminal for outputting a voltage signal, said output terminal being connected to said voltage controlled oscillator, the frequency of said output signal being influenced by said voltage signal, wherein said charge-pump circuit includes: a first analog switch connected between a high-potential power supply and said output terminal, said first analog switch being controlled based on said first phase difference signal, said first analog switch being composed of a pair of PMOS and NMOS transistors connected in parallel; and a second analog switch connected between said output terminal and a low-potential power supply, said second analog switch being controlled based on said second phase difference signal., said second analog switch being composed of a pair of PMOS and NMOS transistors connected in parallel.
Claim 9
Dependent Claim
126 words
A charge-pump circuit for use in a PLL frequency synthesizer circuit, the charge-pump circuit being operated based on first and second phase difference signals to be fed thereto, comprising: an output terminal for outputting a voltage signal; a first analog switch connected between a high-potential power supply and said output terminal, said first analog switch being controlled based on the first phase difference signal, said first analog switch being composed of a pair of PMOS and NMOS transistors connected in parallel; and a second analog switch connected between said output terminal and a low-potential power supply, said second analog switch being controlled based on the second phase difference signal, said second analog switch being composed of a pair of PMOS and NMOS transistors connected in parallel.
Claim 10
Dependent Claim
126 words
A charge-pump circuit for use in a PLL frequency synthesizer circuit, the charge-pump circuit being operated based on first and second phase difference signals to be fed thereto, comprising: an output terminal for outputting a voltage signal; a first analog switch connected between a high-potential power supply and said output terminal, said first analog switch being controlled based on the first phase difference signal, said first analog switch being composed of a pair of PMOS and NMOS transistors connected in parallel; and a second analog switch connected between said output terminal and a low-potential power supply, said second analog switch being controlled based on the second phase difference signal, said second analog switch being composed of a pair of PMOS and NMOS transistors connected in parallel.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-09 | 2000-01-08 | 2000-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-09 | 2004-01-08 | 2004-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-09 | 2008-01-08 | 2008-07-09 | $7700.00 | Window Closed / Lapsed |