Semiconductor analog switch circuit using MOS transistors

Claim 2

A semiconductor analog switch circuit device comprising: input means (IN) for receiving an input signal; output means (OUT) for providing an output signal; and a first series circuit (Tp ll , T P12 ; T P13 , T P14 ) including first and second MOS transistors (T P11 ), (T P12 ); (T P13 ), (T P14 ), characterized in that these is further included a second series circuit (T N11' T N12 ; T P15' T P16 ) having third and fourth transistors (T N11 ), (T N12 ); (T P15 ), (Tp l6 ) and connected in parallel to said first series circuit (T P11 , T P12 ), (T P13' T P14 ), said input means (IN) is connected to one of parallel junctions of said first and second series circuits (T P11 . T P12 ), (Tpl3), (T P14 ); (T N11' T N12 ), (T P15 , T P16 ), and said output means (OUT) is connected to the other parallel junction.

Claim 3

A semiconductor analog switch circuit device according to claim 1, wherein said first and second MOS transistors (T P11 ), (T P12 ) are of a first channel type ( P ), said third and fourth transistors (T N11 ), ( T N12 ) are of a second channel type (N), and the pairs of said first and second MOS transistors (Tp ll ), (T P12 ) and of said third and fourth MOS transistors (T N11 , T N12 ) are respectively controlled by control signals (CK), (CK) with opposite phases.

Claim 4

A semiconductor analog switch circuit device according to claim 2, characterized in that said first to fourth MOS transistors (T P11 ), (T P12 ), (T N11 ), ( T N12) are substantially equal to each other in channel width.

Claim 5

A semiconductor analog switch circuit device according to claim 1, characterized in that said first to fourth MOS transistors (Tp l3 ), (T P14 ), (T P15 ), ( T pl6) are all of the same channel type (P), and the pairs of said first and third transistors (Tp l3 ), (Tp l5 ) and of said second and fourth MOS transistors (T P14 ), (T P16 ) are respectively controlled by control signals (CK), (CK) with opposite phases.

Claim 6

A semiconductor analog switch circuit device according to claim 4, characterized in that a channel width of each of said first and third MOS transistors (T P13 ), (T P15 ) is substantially twice that of each of said second and fourth MOS transistors (T P14 ), (T P16 ).

Claim 7

A semiconductor analog switch circuit device comprising: input means (IN) for receiving an input signal; output means (OUT) for providing an output signal; and a first series circuit (T P11' Tp 12 ) including first and second MOS transistors (T P11 ), (Tp12) of a first channel type (P) controlled by a first control signal (CK), characterized in that there is further included a second series circuit (T N11 , T N12 ) having third and fourth MOS transistors (T N11 ), (T N12 ) which is connected in parallel to said first series circuit (Tp ll , Tp l2 ) and controlled by a second control signal (CK) with opposite phase to that of said first control signal (CK), said input means (IN) is connected to one of parallel junctions of said first and second series circuits ( Tp ll, T P12 ), (T N11' T N12 ), and said output means (OUT) is connected to the other parallel junction.

Claim 8

A semiconductor analog switch circuit device comprising: input means (IN) for receiving an input signal; output means (OUT) for providing an output signal; and a first series circuit (T P11' Tp 12 ) including first and second MOS transistors (T P11 ), (Tp12) of a first channel type (P) controlled by a first control signal (CK), characterized in that there is further included a second series circuit (T N11 , T N12 ) having third and fourth MOS transistors (T N11 ), (T N12 ) which is connected in parallel to said first series circuit (Tp ll , Tp l2 ) and controlled by a second control signal (CK) with opposite phase to that of said first control signal (CK), said input means (IN) is connected to one of parallel junctions of said first and second series circuits ( Tp ll, T P12 ), (T N11' T N12 ), and said output means (OUT) is connected to the other parallel junction.

Claim 9

A semiconductor analog switch circuit device according to claim 6, characterized in that said first to fourth MOS transistors (Tpll), ( Tp l2), (TN 11 ), (T N12 ) are substantially equal to each other in channel width.

Claim 10

A semiconductor analog switch circuit device comprising: input means (IN) for receiving an input signal; output means (OUT) for providing an output signal; a first series circuit (T P13 , Tp 14 ) including a first MOS transistor (Tp l3 ) controlled by a first control signal (CK) and a second MOS transistor (Tp 14 ) controlled by a second control signal (CK) with opposite phase; characterized in that there is further included a second series circuit (T P15 , Tp 16 ) having a third MOS5 transistor (T P15 ) controlled by said first control signal (CK) and a fourth MOS transistor (Tp16) controlled by said second control signal (CK), said second series circuit (T P15 , T P16 ) being connected in parallel to said first series circuit (T P13 , Tp l4 ), said input means (IN) is connected to one of parallel junctions of said first and second series circuits (T P13' T P14 ), (T P15' T P16 ), and said output means (OUT) is connected to the other parallel junction.

Claim 11

A semiconductor analog switch circuit device comprising: input means (IN) for receiving an input signal; output means (OUT) for providing an output signal; a first series circuit (T P13 , Tp 14 ) including a first MOS transistor (Tp l3 ) controlled by a first control signal (CK) and a second MOS transistor (Tp 14 ) controlled by a second control signal (CK) with opposite phase; characterized in that there is further included a second series circuit (T P15 , Tp 16 ) having a third MOS5 transistor (T P15 ) controlled by said first control signal (CK) and a fourth MOS transistor (Tp16) controlled by said second control signal (CK), said second series circuit (T P15 , T P16 ) being connected in parallel to said first series circuit (T P13 , Tp l4 ), said input means (IN) is connected to one of parallel junctions of said first and second series circuits (T P13' T P14 ), (T P15' T P16 ), and said output means (OUT) is connected to the other parallel junction.

Claim 12

A semiconductor analog switch circuit device according to claim 8, characterized in that a channel width of each of said first and third MOS transistors (T P13 ), (Tp15) is substantially twice that of each of said second and fourth MOS transistors (T P14 ), (T P16 ).