US5124594A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital phase comparator for use in a phase lock loop
Assignee: Sony Corp
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Filing: 1991-07-17
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Granted: 1992-06-23
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Expires: 2011-07-17
Abstract
Abstract A Digital Phase Comparator has a simplified logic circuit in which Nand Circuits provide UP and DOWN signals containing phase information about E and F signals.
Inventors
- 👤 Hiroshi Numata
- 👤 Tamotsu Kogo
- 👤 Shinichi Kitazono
- 👤 Fumio Ishikawa
- 👤 Akira Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:14
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/12; H03; H03D; H03D13/00; H03D13/003; H03D13/004; H03K; H03K5/00; H03K5/22; H03K5/26; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891; H03L7/16; H03L7/18; H03L7/183; H03L7/193
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
228 words
A digital type phase comparator comparing in phase an E signal from a reference signal oscillator with an F signal from a voltage-controlled oscillator and outputting an UP signal or a DOWN signal, the logic level of said UP signal or said DOWN signal being controlled according to the phase difference between said E signal and said F signal, said digital type phase comparator comprising: a first NAND circuit to which said E signal is supplied; a fourth NAND circuit to which said F signal is supplied; a second NAND circuit to which the output of said first NAND circuit is supplied and whose output is sent to said first NAND circuit; a third NAND circuit to which the output of said fourth NAND circuit is supplied and whose output is sent to said fourth NAND circuit; and a fifth NAND circuit to which said E signal, said F signal, the output of said first NAND circuit and the output of said fourth NAND circuit are supplied; wherein the output of said fifth NAND circuit is fed to said second NAND circuit and said third NAND circuit; and wherein the output of said second NAND circuit and that of said third NAND circuit are output to the outside as said UP signal and said DOWN signal containing the phase information about said E signal and said F signal.
Claim 2
Dependent Claim
228 words
A digital type phase comparator comparing in phase an E signal from a reference signal oscillator with an F signal from a voltage-controlled oscillator and outputting an UP signal or a DOWN signal, the logic level of said UP signal or said DOWN signal being controlled according to the phase difference between said E signal and said F signal, said digital type phase comparator comprising: a first NAND circuit to which said E signal is supplied; a fourth NAND circuit to which said F signal is supplied; a second NAND circuit to which the output of said first NAND circuit is supplied and whose output is sent to said first NAND circuit; a third NAND circuit to which the output of said fourth NAND circuit is supplied and whose output is sent to said fourth NAND circuit; and a fifth NAND circuit to which said E signal, said F signal, the output of said first NAND circuit and the output of said fourth NAND circuit are supplied; wherein the output of said fifth NAND circuit is fed to said second NAND circuit and said third NAND circuit; and wherein the output of said second NAND circuit and that of said third NAND circuit are output to the outside as said UP signal and said DOWN signal containing the phase information about said E signal and said F signal.
Claim 3
Dependent Claim
338 words
A digital type phase comparator comparing in phase an E signal from a reference signal oscillator with an F signal from a voltage-controlled oscillator and outputting and UP signal or a DOWN signal, the logic level of said UP signal or said DOWN signal being controlled according to the phase difference between said E signal and said F signal, said digital type phase comparator comprising: a first NAND circuit to which said E signal is supplied; a fourth NAND circuit to which said F signal is supplied; a second NAND circuit to which the output of said first NAND circuit is supplied and whose output is sent to said first NAND circuit; a third NAND circuit to which the output of said fourth NAND circuit is supplied and whose output is sent to said fourth NAND circuit; and a fifth NAND circuit to which said E signal, said F signal, the output of said first NAND circuit and the output of said fourth NAND circuit are supplied, wherein the output of said fifth NAND circuit is supplied to said second NAND circuit and to said third NAND circuit; an upstream circuit for forwarding downstream the output of said second NAND circuit and that of said third NAND circuit as said UP signal and said DOWN signal containing the phase information about said E signal and said F signal; a first logic circuit to which said UP signal is supplied; a second logic circuit to which said DOWN signal is supplied; and an exclusive OR or NOR circuit to which said UP signal and said DOWN signal are supplied; wherein the output of said exclusive OR or NOR circuit is fed to said first and said second logic circuits and the output of said first logic circuit and that of said second logic circuit are sent out of said phase comparator as an improved UP signal and an improved DOWN signal, said improved UP and DOWN signals containing the phase information about said E signal and said F signal.
Claim 4
Dependent Claim
338 words
A digital type phase comparator comparing in phase an E signal from a reference signal oscillator with an F signal from a voltage-controlled oscillator and outputting and UP signal or a DOWN signal, the logic level of said UP signal or said DOWN signal being controlled according to the phase difference between said E signal and said F signal, said digital type phase comparator comprising: a first NAND circuit to which said E signal is supplied; a fourth NAND circuit to which said F signal is supplied; a second NAND circuit to which the output of said first NAND circuit is supplied and whose output is sent to said first NAND circuit; a third NAND circuit to which the output of said fourth NAND circuit is supplied and whose output is sent to said fourth NAND circuit; and a fifth NAND circuit to which said E signal, said F signal, the output of said first NAND circuit and the output of said fourth NAND circuit are supplied, wherein the output of said fifth NAND circuit is supplied to said second NAND circuit and to said third NAND circuit; an upstream circuit for forwarding downstream the output of said second NAND circuit and that of said third NAND circuit as said UP signal and said DOWN signal containing the phase information about said E signal and said F signal; a first logic circuit to which said UP signal is supplied; a second logic circuit to which said DOWN signal is supplied; and an exclusive OR or NOR circuit to which said UP signal and said DOWN signal are supplied; wherein the output of said exclusive OR or NOR circuit is fed to said first and said second logic circuits and the output of said first logic circuit and that of said second logic circuit are sent out of said phase comparator as an improved UP signal and an improved DOWN signal, said improved UP and DOWN signals containing the phase information about said E signal and said F signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-23 | 1995-12-23 | 1996-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-23 | 1999-12-23 | 2000-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-23 | 2003-12-23 | 2004-06-23 | $7700.00 | Window Closed / Lapsed |