Synchronized clock generating apparatus

Claim 2

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying a selected one of said delayed clock signals to said selected clock output and a feedback signal to a selected feedback output of said feedback outputs in response to a first one of said flip-flop output signals switching to said reset state; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 3

A synchronized clock generating apparatus according to claim 1, further comprising a plurality of inhibit paths for connecting said feedback outputs to said disabling input for inhibiting from being transmitted to said delaying elements any of said delayed clock signals succeeding said selected one of said delayed clock signals and wherein said plurality of delay elements have disabling inputs.

Claim 4

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying a first one of said delayed clock signals having a transition after a transition of said trigger signal to said selected clock output and a feedback signal to a selected feedback output of said feedback outputs in response to a first one of said flip-flop output signals switching to said reset state; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 5

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying a first one of said delayed clock signals having a transition after a transition of said trigger signal to said selected clock output and a feedback signal to a selected feedback output of said feedback outputs in response to a first one of said flip-flop output signals switching to said reset state; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 6

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying to said selected clock output a selected one of said delayed clock signals and a feedback signal to a selected feedback output of said feedback outputs in response to a first one of said flip-flop output signals switching to said reset state; said selected one of said delayed clock signals having a transition succeeding a first one of said delayed clock signals having a transition after a transition of said trigger signal, by a predetermined period; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 7

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying to said selected clock output a selected one of said delayed clock signals and a feedback signal to a selected feedback output of said feedback outputs in response to a first one of said flip-flop output signals switching to said reset state; said selected one of said delayed clock signals having a transition succeeding a first one of said delayed clock signals having a transition after a transition of said trigger signal, by a predetermined period; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 8

A synchronized clock generating apparatus according to claim 4, further comprising a plurality of inhibit paths for connecting said feedback outputs to said disabling input to inhibit from being transmitted to said delaying elements any of said delayed clock signals succeeding said selected one of said delayed clock signals and wherein said plurality of delay elements have disabling inputs.

Claim 9

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying to said selected clock output a selected one of said delayed clock signals and a feedback signal to a selected feedback output of said feedback outputs in response to a first one of said flip-flop output signals switching to said reset state; said selected one of said delayed clock signals having a transition preceding a first one of said delayed clock signals having a transition after a transition of said trigger signal, by a predetermined period; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 10

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying to said selected clock output a selected one of said delayed clock signals and a feedback signal to a selected feedback output of said feedback outputs in response to a first one of said flip-flop output signals switching to said reset state; said selected one of said delayed clock signals having a transition preceding a first one of said delayed clock signals having a transition after a transition of said trigger signal, by a predetermined period; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 11

A synchronized clock generating apparatus according to claim 6, further comprising a plurality of inhibit paths for connecting said feedback outputs to said disabling input for inhibiting from being transmitted to said delaying elements any of said delayed clock signals succeeding said selected one of said delayed clock signals and wherein said plurality of delay elements have disabling inputs.

Claim 12

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying to said selected clock output a selected one of said delayed clock signals and a feedback signal to a selected feedback output of said feedback outputs in response to one of said flip-flop output signals switching to said reset state and another one of said flip-flop outputs, preceding said one of said flip-flop output signals, being in said set state; said selected one of said delayed clock signals having a transition with a predetermined relationship to a said one of said delayed clock signals; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 13

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying to said selected clock output a selected one of said delayed clock signals and a feedback signal to a selected feedback output of said feedback outputs in response to one of said flip-flop output signals switching to said reset state and another one of said flip-flop outputs, preceding said one of said flip-flop output signals, being in said set state; said selected one of said delayed clock signals having a transition with a predetermined relationship to a said one of said delayed clock signals; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 14

A synchronized clock generating apparatus according to claim 8 further comprising a plurality of inhibit paths for connecting said feedback outputs to said disabling input for inhibiting from being transmitted to said delaying elements any of said delayed clock signals succeeding said selected one of said delayed clock signals and wherein said plurality of delay elements have disabling inputs.

Claim 15

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; each of said plurality of delaying elements of said delayed clock generating circuit being a semiconductor logic element; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying to said selected clock output a selected one of said delayed clock signals and a feedback signal to a selected feedback output of said feedback outputs in response to one of said flip-flop output signals switching to said reset state and another one of said flip-flop outputs, preceding said one of said flip-flop output signals, being in said set state; said selected one of said delayed clock signals having a transition with a predetermined relationship to a said one of said delayed clock signals; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 16

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; each of said plurality of delaying elements of said delayed clock generating circuit being a semiconductor logic element; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying to said selected clock output a selected one of said delayed clock signals and a feedback signal to a selected feedback output of said feedback outputs in response to one of said flip-flop output signals switching to said reset state and another one of said flip-flop outputs, preceding said one of said flip-flop output signals, being in said set state; said selected one of said delayed clock signals having a transition with a predetermined relationship to a said one of said delayed clock signals; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 17

A synchronized clock generating apparatus comprising: a delayed clock generating circuit, said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; each of said plurality of delaying elements of said delayed clock generating circuit being a semiconductor logic element; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying a selected one of said delayed clock signals to said selected clock output and a feedback signal to a selected feedback output of said feedback outputs in response to a first one of said flip-flop output signals switching to said reset state; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 18

A synchronized clock generating apparatus comprising: a delayed clock generating circuit, said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; each of said plurality of delaying elements of said delayed clock generating circuit being a semiconductor logic element; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying a selected one of said delayed clock signals to said selected clock output and a feedback signal to a selected feedback output of said feedback outputs in response to a first one of said flip-flop output signals switching to said reset state; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 19

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; each one of said plurality of delaying elements of said delayed clock generating circuit being a semiconductor logic element; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying a first one of said delayed clock signals having a transition after a transition of said trigger signal to said selected clock output and a feedback signal to a selected feedback output of said feedback outputs in response to a first one of said flip-flop output signals switching to said reset state; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 20

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; each one of said plurality of delaying elements of said delayed clock generating circuit being a semiconductor logic element; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying a first one of said delayed clock signals having a transition after a transition of said trigger signal to said selected clock output and a feedback signal to a selected feedback output of said feedback outputs in response to a first one of said flip-flop output signals switching to said reset state; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 21

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; each one of said plurality of delaying elements of said delayed clock generating circuit being a semiconductor logic element; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying to said selected clock output a selected one of said delayed clock signals and a feedback signal to a selected feedback output of said feedback outputs in response to a first one of said flip-flop output signals switching to said reset state; said selected one of said delayed clock signals having a transition succeeding a first one of said delayed clock signals having a transition after a transition of said trigger signal, by a predetermined period; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 22

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; each one of said plurality of delaying elements of said delayed clock generating circuit being a semiconductor logic element; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying to said selected clock output a selected one of said delayed clock signals and a feedback signal to a selected feedback output of said feedback outputs in response to a first one of said flip-flop output signals switching to said reset state; said selected one of said delayed clock signals having a transition succeeding a first one of said delayed clock signals having a transition after a transition of said trigger signal, by a predetermined period; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 23

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; each one of said plurality of delaying elements of said delayed clock generating circuit being a semiconductor logic element; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying to said selected clock output a selected one of said delayed clock signals and a feedback signal to a selected feedback output of said feedback outputs in response to a first one of said flip-flop output signals switching to said reset state; said selected one of said delayed clock signals having a transition preceding a first one of said delayed clock signals having a transition after a transition of said trigger signal, by a predetermined period; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.

Claim 24

A synchronized clock generating apparatus comprising: a delayed clock generating circuit; said delayed clock generating circuit including a clock input having a basic clock signal applied thereto; said delayed clock generating circuit including further a plurality of delaying elements connected in series; each one of said plurality of delaying elements of said delayed clock generating circuit being a semiconductor logic element; said plurality of delaying elements being effective for producing a plurality of delayed clock signals each successively delayed relative to said basic clock signal; a plurality of flip-flops, each having a respective one of said plurality of delayed clock signals applied to a first input thereof; said plurality of flip-flops each having a second input with a trigger signal, asynchronous with said basic clock signal, applied thereto; each of said plurality of flip-flops having a third input and a flip-flop output; said plurality of flip-flops receiving said trigger signal and said delayed clock signals such that each flip-flop, of said plurality of flip-flops, switches a flip-flop output signal at said flip-flop output thereof to a reset state from a set state in response to receiving a transition of said respective one of said delayed clock signals after a transition of said trigger signal; a clock selection circuit having a first plurality of inputs receiving said delayed clock signals, each of a second plurality of inputs receiving a respective one of said flip-flop output signals, a plurality of feedback outputs, and a selected clock output; said clock selection circuit applying to said selected clock output a selected one of said delayed clock signals and a feedback signal to a selected feedback output of said feedback outputs in response to a first one of said flip-flop output signals switching to said reset state; said selected one of said delayed clock signals having a transition preceding a first one of said delayed clock signals having a transition after a transition of said trigger signal, by a predetermined period; and feedback means for connecting said feedback outputs to said third input of respective ones of said plurality of flip flops.