Receiver circuit with a bus-keeper feature

Claim 2

A receiver circuit, comprising: an input node, for direct connecting to a tristate bus line; an output node; an inverter, having an input directly connected to said input node and having an output coupled to said output node: a first transistor, having a conduction path directly connected on one side to said input node and coupled on another side to a first bias voltage, and having a control terminal; and a second transistor, having a conduction path directly connected on one, side to said input node and coupled on another side to a second bias voltage, and having a control terminal; wherein the control terminals of said first and second transistors are coupled to the output of said inverter in such a manner that said first transistor is on and said second transistor is off responsive to the logic level at said input node corresponding to said first bias voltage and in such a manner that said second transistor is on and said first transistor is off responsive to the logic level at said input node corresponding to said second bias voltage; and wherein said first and second transistors have drive characteristics which are significantly weaker than said inverter.

Claim 3

The receiver of claim 1, wherein said first and second transistors are field effect transistors.

Claim 4

The receiver of claim 2, wherein said first and second transistors are of first and second conductivity type, respectively, and have their control terminals connected in common to the output of said inverter.

Claim 5

The receiver of claim 3, wherein said inverter comprises first and second inverter transistors of the field effect type, having their source/drain paths connected in series between said first and second bias voltages, having their gates coupled in common to said input node, and having their drains coupled to said output node.

Claim 6

The receiver of claim 4, wherein the width/length ratio of said first transistor is significantly smaller than the width/length ratio of said first inverter transistor; and wherein the width/length ratio of said second transistor is significantly smaller than the width/length ratio of said second inverter transistor.

Claim 7

The receiver of claim 4, wherein the source/drain on resistance of said first transistor is significantly greater than that of said first inverter transistor; and wherein the source/drain on resistance of said second transistor is significantly greater than that of said second inverter transistor.

Claim 8

An electronic system, comprising: a bus line; a driver circuit, for selectively driving said bus line to a first logic state or a second logic state, said driver circuit also having a high impedance output state; and a receiver, having an output node, comprising: an inverter, having an input directly connected to said bus line and having an output coupled to said output node; a first transistor, having a conduction path directly connected on one side to said bus line and coupled on another side to a first bias voltage, and having a control terminal; and a second transistor, having a conduction path directly connected on one side to said bus line and coupled on another side to a second bias voltage, and having a control terminal; wherein said first and second bias voltages correspond to said first and second logic states, respectively; wherein the control terminals of said first and second transistors are coupled to the output of said inverter in such a manner that said first transistor is on and said second transistor is off responsive to said first logic state and said bus line, and in such a manner that said second transistor is on and said first transistor is off responsive to said second logic state at said bus line; and wherein said first and second transistors have drive characteristics which are significantly weaker than said driver circuit.

Claim 9

An electronic system, comprising: a bus line; a driver circuit, for selectively driving said bus line to a first logic state or a second logic state, said driver circuit also having a high impedance output state; and a receiver, having an output node, comprising: an inverter, having an input directly connected to said bus line and having an output coupled to said output node; a first transistor, having a conduction path directly connected on one side to said bus line and coupled on another side to a first bias voltage, and having a control terminal; and a second transistor, having a conduction path directly connected on one side to said bus line and coupled on another side to a second bias voltage, and having a control terminal; wherein said first and second bias voltages correspond to said first and second logic states, respectively; wherein the control terminals of said first and second transistors are coupled to the output of said inverter in such a manner that said first transistor is on and said second transistor is off responsive to said first logic state and said bus line, and in such a manner that said second transistor is on and said first transistor is off responsive to said second logic state at said bus line; and wherein said first and second transistors have drive characteristics which are significantly weaker than said driver circuit.

Claim 10

The system of claim 7, wherein said first and second transistors are field effect transistors.

Claim 11

The system of claim 8, wherein said first and second transistors are of first and second conductivity type, respectively, and have their control terminals connected in common to the output of said inverter.

Claim 12

The system of claim 9, wherein said inverter comprises first and second inverter transistors of the field effect type, having their source/drain paths connected in series between said first and second bias voltages, having their gates coupled in common to said bus line, and having their drains coupled to said output node; wherein the source/drain on resistance of said first transistor is significantly greater than that of said first inverter transistor; and wherein the source/drain on resistance of said second transistor is significantly greater than that of said second inverter transistor.

Claim 13

An electronic system, comprising: a bus line; a driver circuit, for selectively driving said bus line to a first logic state or a second logic state, said driver circuit also having a high impedance output state; and a receiver, having an output node, comprising: an inverter, having an input directly connected to said bus line ant having an output coupled to said output node; a first transistor, having a conduction path directly connected on one side to said bus line and coupled on another side to a first bias voltage, and having a control terminal; and a second transistor, having a conduction path directly connected on one side to said bus line and coupled on another side to a second bias voltage, and having a control terminal; wherein said first and second bias voltages correspond to said first and second logic states, respectively; wherein the control terminals of said first and second transistors are coupled to the output of said inverter in such a manner that said first transistor is on and said second transistor is off responsive to said first logic state and said bus line, and in such a manner that said second transistor is on and said first transistor is off responsive to said second logic state at said bus line; wherein said first and second transistors have drive characteristics which are significantly weaker than said driver circuit; wherein said first and second transistors are field effect transistors; wherein said first and second transistors are of first and second conductivity type, respectively, and have their control terminals connected in common to the output of said inverter; and, wherein said driver circuit is of the push-pull type.

Claim 14

An electronic system, comprising: a bus line; a driver circuit, for selectively driving said bus line to a first logic state or a second logic state, said driver circuit also having a high impedance output state; and a receiver, having an output node, comprising: an inverter, having an input directly connected to said bus line ant having an output coupled to said output node; a first transistor, having a conduction path directly connected on one side to said bus line and coupled on another side to a first bias voltage, and having a control terminal; and a second transistor, having a conduction path directly connected on one side to said bus line and coupled on another side to a second bias voltage, and having a control terminal; wherein said first and second bias voltages correspond to said first and second logic states, respectively; wherein the control terminals of said first and second transistors are coupled to the output of said inverter in such a manner that said first transistor is on and said second transistor is off responsive to said first logic state and said bus line, and in such a manner that said second transistor is on and said first transistor is off responsive to said second logic state at said bus line; wherein said first and second transistors have drive characteristics which are significantly weaker than said driver circuit; wherein said first and second transistors are field effect transistors; wherein said first and second transistors are of first and second conductivity type, respectively, and have their control terminals connected in common to the output of said inverter; and, wherein said driver circuit is of the push-pull type.

Claim 15

The system of claim 11, wherein said driver circuit comprises: a pull-up transistor of the field effect type; and a pull-down transistor of the field effect type; wherein the width/length ratio of said first transistor is significantly smaller than the width/length ratio of said pull-up transistor; and wherein the width/length ratio of said second transistor is significantly smaller than the width/length ratio of said pull-down transistor.

Claim 16

The system of claim 7, wherein said driver circuit and said receiver are disposed on the same integrated circuit.

Claim 17

The system of claim 13, wherein said bus line is disposed on the same integrated circuit as said driver circuit and receiver.

Claim 20

The method of claim 15, further comprising: after said maintaining step, driving said bus line to the opposite logic level from that driven in said first driving step.

Claim 21

The method of claim 15, wherein said first and second transistors are of the field effect type, and have opposite conductivity type from one another.

Claim 22

The method of claim 15, further comprising: after said maintaining step, driving said bus line with a second output driver coupled thereto, said first output driver remaining in said high impedance state.

Claim 23

A receiver circuit, comprising: an input node, for coupling to a tristate bus line; a receiver output node; a first inverter, having an input coupled to said input node and having an output coupled to said output node; a first transistor, having a conduction path coupled on one side to said input node and coupled on another side to a first bias voltage, and having a control terminal; a second transistor, having a conduction path coupled on one side to said input node and coupled on another side to a second bias voltage, and having a control terminal; a latch comprising a first latch transistor and a second latch transistor, having their source/drain paths connected in series between said first and second bias voltages having their gates coupled in common to said receiver output node, and having their drains coupled to said first inverter; and, a second inverter having an input coupled to an output of said latch, and an output coupled to said receiver output node; wherein the control terminals of said first and second transistors are coupled to the output of said inverter in such a manner that said first transistor is on and said second transistor is off responsive to the logic level at said input node corresponding to said first bias voltage, and in such a manner that said second transistor is on and said first transistor is off responsive to the logic level at said input node corresponding to said second bias voltage; and wherein said first and second transistors have drive characteristics which are significantly weaker than said inverter.

Claim 24

A receiver circuit, comprising: an input node, for coupling to a tristate bus line; a receiver output node; a first inverter, having an input coupled to said input node and having an output coupled to said output node; a first transistor, having a conduction path coupled on one side to said input node and coupled on another side to a first bias voltage, and having a control terminal; a second transistor, having a conduction path coupled on one side to said input node and coupled on another side to a second bias voltage, and having a control terminal; a latch comprising a first latch transistor and a second latch transistor, having their source/drain paths connected in series between said first and second bias voltages having their gates coupled in common to said receiver output node, and having their drains coupled to said first inverter; and, a second inverter having an input coupled to an output of said latch, and an output coupled to said receiver output node; wherein the control terminals of said first and second transistors are coupled to the output of said inverter in such a manner that said first transistor is on and said second transistor is off responsive to the logic level at said input node corresponding to said first bias voltage, and in such a manner that said second transistor is on and said first transistor is off responsive to the logic level at said input node corresponding to said second bias voltage; and wherein said first and second transistors have drive characteristics which are significantly weaker than said inverter.

Claim 25

The receiver of claim 19, wherein: the width/length ratio of said first latch transistor is larger than the width length ratio of said first transistor and is smaller than the width/length ratio of said first inverter transistor; and the width/length ratio of said second latch transistor is larger than the width length ratio of said second transistor and is smaller than the width/length ratio of said second inverter transistor.