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US5530674A
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Structure capable of simultaneously testing redundant and non-redundant memory elements during stress testing of an integrated circuit memory device
Assignee: STMicroelectronics lnc USA
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Filing: 1994-04-29
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Granted: 1996-06-25
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Expires: 2014-04-29
Abstract
Abstract The redundant elements of an integrated circuit memory device having a plurality of redundant and non-redundant elements such as rows, columns, wordlines, and blocks, may be selectively enabled during a stress test mode so that both redundant elements and non-redundant elements may be stress tested concurrently. Enabling capabilities contained within the redundant element circuitry selectively enables the redundant elements when a stress test signal is equal to a predetermined value, indicative of a stress test mode.
Inventors
- 👤 David C. McClure
- 👤 Thomas A. Teel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:07
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/24; G11C29/50; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41
Claims Analysis
Total Claims: 44
Claim 1
Independent Claim
125 words
An integrated circuit memory device, comprising: a plurality of non-redundant memory elements, arranged in a plurality of rows and a plurality of columns; at least one redundant memory element, suitable for replacing a non-redundant memory element that is defective; and enabling means, coupled to said plurality of non-redundant memory elements and said at least one redundant memory element and contained within a redundant element circuit, for selectively enabling the at least one redundant memory element when a stress test signal is equal to a first predetermined logic level indicative of a stress test mode such that the at least one redundant memory element and the plurality of non-redundant memory elements may be concurrently stress tested when the plurality of non-redundant memory elements are also enabled.
Claim 2
Dependent Claim
125 words
An integrated circuit memory device, comprising: a plurality of non-redundant memory elements, arranged in a plurality of rows and a plurality of columns; at least one redundant memory element, suitable for replacing a non-redundant memory element that is defective; and enabling means, coupled to said plurality of non-redundant memory elements and said at least one redundant memory element and contained within a redundant element circuit, for selectively enabling the at least one redundant memory element when a stress test signal is equal to a first predetermined logic level indicative of a stress test mode such that the at least one redundant memory element and the plurality of non-redundant memory elements may be concurrently stress tested when the plurality of non-redundant memory elements are also enabled.
Claim 3
Dependent Claim
20 words
The device of claim 1, wherein during the stress test mode the enabling means turns on a plurality of wordlines.
Claim 4
Dependent Claim
20 words
The device of claim 2, wherein the plurality of wordlines comprises all the wordlines of the integrated circuit memory device.
Claim 5
Dependent Claim
20 words
The device of claim 1, wherein during the stress test mode the enabling means turns on a plurality of columns.
Claim 6
Dependent Claim
20 words
The device of claim 4, wherein the plurality of columns comprises all the columns of the integrated circuit memory device.
Claim 7
Dependent Claim
18 words
The device of claim 1, wherein the redundant memory element is arranged in a plurality of redundant rows.
Claim 8
Dependent Claim
28 words
The device of claim 6, wherein the enabling means is used to selectively enable the redundant rows, and the enabling means is contained within a row redundancy circuit.
Claim 9
Dependent Claim
15 words
The device of claim 7, wherein the row redundancy circuit comprises a latchable redundant element.
Claim 10
Dependent Claim
38 words
The device of claim 8, wherein the latchable redundant element is placed in a latched mode during the stress test mode, and the logic state of the latchable redundant element is forced to a second predetermined logic level.
Claim 11
Dependent Claim
18 words
The device of claim 1, wherein the redundant memory element is arranged in a plurality of redundant columns.
Claim 12
Dependent Claim
29 words
The device of claim 10, wherein the enabling means is used to selectively enable the redundant columns, and the enabling means is contained within a redundant column decoder circuit.
Claim 13
Dependent Claim
20 words
The device of claim 1, wherein the redundant memory element is grouped into at least one redundant memory array block.
Claim 14
Dependent Claim
31 words
The device of claim 12, wherein the enabling means is used to selectively enable the redundant memory array block, and the enabling means is contained within a redundant block decoder circuit.
Claim 15
Dependent Claim
21 words
The device of claim 1, wherein the plurality of non-redundant memory elements are grouped into a plurality of memory array blocks.
Claim 16
Dependent Claim
21 words
The device of claim 1, wherein the redundant memory element and the non-redundant memory elements are enabled at a pre-repair step.
Claim 17
Dependent Claim
31 words
The device of claim 15, wherein enabling the redundant memory element and the non-redundant memory elements at the pre-repair step allows recovery of stress test yield fallout at a repair step.
Claim 18
Dependent Claim
21 words
The device of claim 1, wherein the redundant memory element and the non-redundant memory elements are enabled at a post-repair step.
Claim 19
Dependent Claim
28 words
The device of claim 1, wherein the enabling means allows for selectively choosing the redundant memory element which is swapped in to replace a defective non-redundant memory element.
Claim 20
Dependent Claim
23 words
The device of claim 1, wherein the enabling means is used to control a master redundant enable element for the redundant memory element.
Claim 21
Dependent Claim
20 words
The device of claim 1, wherein the redundant memory element and the non-redundant memory elements may be stress tested concurrently.
Claim 22
Dependent Claim
18 words
The device of claim 1, wherein the integrated circuit memory device is a static random access memory (SRAM).
Claim 23
Independent Claim
138 words
A method for enabling and stress testing one or more redundant memory elements of an integrated circuit memory device, comprising the steps of: selectively enabling at least one redundant memory element of the integrated circuit memory device, through an enabling means contained within a redundant element circuit, when a stress test signal is equal to a first predetermined logic level, wherein the integrated circuit memory device comprises a plurality of non-redundant memory elements and the redundant memory element, wherein the plurality of non-redundant memory elements are arranged in a plurality of rows and a plurality of columns, and the redundant memory element is suitable for replacing a non-redundant memory element that is defective; and concurrently stress testing the redundant memory element and the plurality of non-redundant memory elements when the plurality of non-redundant memory elements are also enabled.
Claim 24
Independent Claim
138 words
A method for enabling and stress testing one or more redundant memory elements of an integrated circuit memory device, comprising the steps of: selectively enabling at least one redundant memory element of the integrated circuit memory device, through an enabling means contained within a redundant element circuit, when a stress test signal is equal to a first predetermined logic level, wherein the integrated circuit memory device comprises a plurality of non-redundant memory elements and the redundant memory element, wherein the plurality of non-redundant memory elements are arranged in a plurality of rows and a plurality of columns, and the redundant memory element is suitable for replacing a non-redundant memory element that is defective; and concurrently stress testing the redundant memory element and the plurality of non-redundant memory elements when the plurality of non-redundant memory elements are also enabled.
Claim 25
Dependent Claim
19 words
The method of claim 22, wherein the redundant memory element and the non-redundant memory elements are stress tested concurrently.
Claim 26
Dependent Claim
20 words
The method of claim 22, wherein during the stress test mode the enabling means turns on a plurality of wordlines.
Claim 27
Dependent Claim
20 words
The method of claim 24, wherein the plurality of wordlines comprises all the wordlines of the integrated circuit memory device.
Claim 28
Dependent Claim
20 words
The method of claim 22, wherein during the stress test mode the enabling means turns on a plurality of columns.
Claim 29
Dependent Claim
20 words
The method of claim 26, wherein the plurality of columns comprises all the columns of the integrated circuit memory device.
Claim 30
Dependent Claim
18 words
The method of claim 22, wherein the redundant memory element is arranged in a plurality of redundant rows.
Claim 31
Dependent Claim
28 words
The method of claim 28, wherein the enabling means is used to selectively enable the redundant rows, and the enabling means is contained within a row redundancy circuit.
Claim 32
Dependent Claim
15 words
The method of claim 29, wherein the row redundancy circuit comprises a latchable redundant element.
Claim 33
Dependent Claim
38 words
The method of claim 30, wherein the latchable redundant element is placed in a latched mode during the stress test mode, and the logic state of the latchable redundant element is forced to a second predetermined logic level.
Claim 34
Dependent Claim
18 words
The method of claim 22, wherein the redundant memory element is arranged in a plurality of redundant columns.
Claim 35
Dependent Claim
29 words
The method of claim 32, wherein the enabling means is used to selectively enable the redundant columns, and the enabling means is contained within a redundant column decoder circuit.
Claim 36
Dependent Claim
20 words
The method of claim 22, wherein the redundant memory element is grouped into at least one redundant memory array block.
Claim 37
Dependent Claim
31 words
The method of claim 34, wherein the enabling means is used to selectively enable the redundant memory array block, and the enabling means is contained within a redundant block decoder circuit.
Claim 38
Dependent Claim
21 words
The method of claim 22, wherein the plurality of non-redundant memory elements are grouped into a plurality of memory array blocks.
Claim 39
Dependent Claim
21 words
The method of claim 22, wherein the redundant memory element and the non-redundant memory elements are enabled at a pre-repair step.
Claim 40
Dependent Claim
31 words
The method of claim 37, wherein enabling the redundant memory element and the non-redundant memory elements at the pre-repair step allows recovery of stress test yield fallout at a repair step.
Claim 41
Dependent Claim
21 words
The method of claim 22, wherein the redundant memory element and the non-redundant memory elements are enabled at a post-repair step.
Claim 42
Dependent Claim
29 words
The method of claim 22, wherein the enabling means allows for selectively choosing the redundant memory element which will be swapped in to replace a defective non-redundant memory element.
Claim 43
Dependent Claim
23 words
The method of claim 22, wherein the enabling means is used to control a master redundant enable element for the redundant memory element.
Claim 44
Dependent Claim
18 words
The method of claim 22, wherein the integrated circuit memory device is a static random access memory (SRAM).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-25 | 1999-12-25 | 2000-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-25 | 2003-12-25 | 2004-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-25 | 2007-12-25 | 2008-06-25 | $7700.00 | Window Closed / Lapsed |