Bus driver/receiver circuitry and systems and methods using the same

Claim 2

Data transmission circuitry comprising: a transmission line; driver circuitry coupled to said transmission line, said driver circuitry setting said transmission line to a low transmission voltage level during transmission of information of a first logic state and setting said transmission line to a higher transmission voltage during transmission of information of a second logic state; and receiver circuitry operable to compare voltage on said transmission line with a static reference voltage substantially equal to a predetermined fraction of said higher transmission voltage and, in response to said comparison, latch an output to a corresponding logic state, said receiver circuitry latching said output in an output high logic state to an output voltage which is a multiple of said higher transmission voltage.

Claim 3

The data transmission circuitry of claim 1 wherein said output voltage is approximately twice said higher transmission voltage.

Claim 4

The data transmission circuitry of claim 1 wherein said receiver circuitry comprises: latching circuitry including: a first transistor of a first type having a first source/drain coupled to a supply voltage rail at said multiple of said higher transmission voltage; a second transistor of a second type having a first source/drain coupled to a second source/drain of said first transistor and a second source/drain coupled to ground; a third transistor of said first type having a first source/drain coupled to said supply voltage rail; and a fourth transistor of said second type having a first source/drain coupled to a second source/drain of said third transistor and a second source/drain coupled to ground; a first control transistor having a gate coupled to said transmission liner a first source/drain coupled to gates of said first and second transistors of said latching circuitry and said second source/drain of said third transistor of said latching circuitry, and a second source/drain coupled to ground; a second control transistor having a gate coupled to said reference voltage, a first source/drain coupled to gates of said third and fourth transistors of said latching circuitry and said second source/drain of said first transistor of said latching circuitry, and a second source/drain coupled to ground; and wherein a node at the coupling of said second source/drain of said third transistor and said first source/drain of said fourth transistor forms said output.

Claim 5

The data transmission circuitry of claim 3 wherein said first type comprises p-type and said second type comprises n-type.

Claim 6

The data transmission circuitry of claim 1 wherein said driver circuitry comprises an inverting driver.

Claim 7

The data transmission circuitry of claim 1 wherein said driver circuitry comprises: a first transistor of said first type having a current path for coupling said transmission line with a voltage supply rail at said higher transmission voltage; a second transistor of said second type having a current path for coupling said transmission line with a low voltage; and wherein respective gates of said first and second transistors of said driver circuitry are coupled together to form a driver input and a node at a coupling of said current paths of said first and second transistors of said driver circuitry forming a driver output for coupling to said transmission line.

Claim 8

Line driver/receiver circuitry for transferring information across a conductive line comprising: a driver for receiving input information having a first voltage swing between a low voltage and a first supply voltage and driving said conductive line with transmission information having a second voltage swing between said low voltage and a second supply voltage, said second supply voltage being less than said first supply voltage; and a receiver for receiving said transmission information having said second voltage swing from said conductive line and outputting output information having a third voltage swing substantially equal to said first voltage swing, said receiver comprising: a first transistor of a first type having a first source/drain coupled to a supply voltage rail at said first supply voltage; a second transistor of a second type having a first source/drain coupled to a second source/drain of said first transistor and a second source/drain coupled to ground; a third transistor of said first type having a first source/drain coupled to said supply voltage rail; a fourth transistor of said second type having a first source/drain coupled to a second source/drain of said third transistor and a second source/drain coupled to ground, wherein a node at the coupling of said second source/drain of said third transistor and said first source/drain of said fourth transistor forms an output of said receiver; a fifth transistor having a gate coupled to said line, a first source/drain coupled to gates of said first and second transistors and said second source/drain of said third transistor, and a second source/drain coupled to ground; and a sixth transistor having a gate coupled to a reference voltage substantially equal to a predetermined fraction of the second supply voltage, a first source/drain coupled to gates of said third and fourth transistors and said second source/drain of said first transistor, and a second source/drain coupled to ground.

Claim 9

Line driver/receiver circuitry for transferring information across a conductive line comprising: a driver for receiving input information having a first voltage swing between a low voltage and a first supply voltage and driving said conductive line with transmission information having a second voltage swing between said low voltage and a second supply voltage, said second supply voltage being less than said first supply voltage; and a receiver for receiving said transmission information having said second voltage swing from said conductive line and outputting output information having a third voltage swing substantially equal to said first voltage swing, said receiver comprising: a first transistor of a first type having a first source/drain coupled to a supply voltage rail at said first supply voltage; a second transistor of a second type having a first source/drain coupled to a second source/drain of said first transistor and a second source/drain coupled to ground; a third transistor of said first type having a first source/drain coupled to said supply voltage rail; a fourth transistor of said second type having a first source/drain coupled to a second source/drain of said third transistor and a second source/drain coupled to ground, wherein a node at the coupling of said second source/drain of said third transistor and said first source/drain of said fourth transistor forms an output of said receiver; a fifth transistor having a gate coupled to said line, a first source/drain coupled to gates of said first and second transistors and said second source/drain of said third transistor, and a second source/drain coupled to ground; and a sixth transistor having a gate coupled to a reference voltage substantially equal to a predetermined fraction of the second supply voltage, a first source/drain coupled to gates of said third and fourth transistors and said second source/drain of said first transistor, and a second source/drain coupled to ground.

Claim 10

The circuitry of claim 7 wherein said information comprises data.

Claim 11

The circuitry of claim 7 wherein said information comprises addresses.

Claim 12

The circuitry of claim 7 wherein said second supply voltage is a fraction of said first supply voltage.

Claim 13

The circuitry of claim 7 wherein said second supply voltage is approximately one half said first supply voltage.

Claim 14

The circuitry of claim 7 and further comprising: a seventh transistor of said first type having a current path coupling said first source/drain of said fifth transistor with said gates of said first and second transistors and said second source/drain of said third transistor, and a gate coupled to receive a clock signal; and a eighth transistor of said first type having a current path coupling said first source/drain of said sixth transistor with said gates of said third and fourth transistors and said second source/drain of first transistor, and a gate coupled to receive said clock signal.

Claim 15

The circuitry of claim 7 and further comprising a transistor of said first type having a first source/drain coupled to gates of said third and fourth transistors and said second source/drain of said first transistor, a second source/drain coupled to ground, and a gate coupled to receive a complementary signal clock signal.

Claim 16

A data processing system comprising: a transmission line; a first block of circuitry including a driver for driving said line with a first voltage swing between a low voltage and a predetermined fraction of a system supply voltage; and a second block of circuitry including a receiver for receiving data at said first voltage swing from said line and outputting data with a second voltage swing between said low voltage and said system supply voltage, said receiver comprising: a first transistor of a first type having a first source/drain coupled to a supply voltage rail at said system supply voltage; a second transistor of a second type having a first source/drain coupled to a second source/drain of said first transistor and a second source/drain coupled to ground; a third transistor of said first type having a first source/drain coupled to said supply voltage rail; a fourth transistor of said second type having a first source/drain coupled to a second source/drain of said third transistor and a second source/drain coupled to ground, wherein a node at the coupling of said second source/drain of said third transistor and said first source/drain of said fourth transistor forms an output of said receiver; a fifth transistor having a gate coupled to said line, a first source/drain coupled to gates of said first and second transistors and said second source/drain of said third transistor, and a second source/drain coupled to ground; and a sixth transistor having a gate coupled to a reference voltage of a fraction of said predetermined fraction of said system supply voltage, a first source/drain coupled to gates of said third and fourth transistors and said second source/drain of said first transistor, and a second source/drain coupled to ground.

Claim 17

A data processing system comprising: a transmission line; a first block of circuitry including a driver for driving said line with a first voltage swing between a low voltage and a predetermined fraction of a system supply voltage; and a second block of circuitry including a receiver for receiving data at said first voltage swing from said line and outputting data with a second voltage swing between said low voltage and said system supply voltage, said receiver comprising: a first transistor of a first type having a first source/drain coupled to a supply voltage rail at said system supply voltage; a second transistor of a second type having a first source/drain coupled to a second source/drain of said first transistor and a second source/drain coupled to ground; a third transistor of said first type having a first source/drain coupled to said supply voltage rail; a fourth transistor of said second type having a first source/drain coupled to a second source/drain of said third transistor and a second source/drain coupled to ground, wherein a node at the coupling of said second source/drain of said third transistor and said first source/drain of said fourth transistor forms an output of said receiver; a fifth transistor having a gate coupled to said line, a first source/drain coupled to gates of said first and second transistors and said second source/drain of said third transistor, and a second source/drain coupled to ground; and a sixth transistor having a gate coupled to a reference voltage of a fraction of said predetermined fraction of said system supply voltage, a first source/drain coupled to gates of said third and fourth transistors and said second source/drain of said first transistor, and a second source/drain coupled to ground.

Claim 18

The system of claim 14 wherein said first block of circuitry includes a state machine.

Claim 19

The system of claim 14 wherein said second block of circuitry includes a memory.

Claim 20

The system of claim 14 wherein said transmission line comprises one of a plurality of transmission lines forming a bus.

Claim 21

The system of claim 14 wherein said predetermined fraction is substantially one-half.

Claim 22

The system of claim 14 wherein said transmission line and said first and second blocks of circuitry are disposed on a single chip.

Claim 25

The method of claim 20 wherein the predetermined fraction of the supply voltage is approximately one-half.