Patent US5529941A successfully refreshed from Google Patents.
US5529941A
Expired / Lapsed
US
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Method for making an integrated circuit structure
Assignee: Philips Semiconductors Inc
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Filing: 1994-03-28
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Granted: 1996-06-25
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Expires: 2014-03-28
Abstract
Abstract A method for making an integrated circuit in accordance with the present invention comprises fabricating at least one functional MOSFET with a hot electron resistant structure including a lightly doped drain, fabricating at least one output MOSFET with an ESD resistant structure including a gate means without associated spacers, and electrically coupling at least one functional MOSFET to at least one output MOSFET. An integrated circuit structure in accordance with the present invention includes at least one functional MOSFET having a hot electron resistant structure including a LDD drain, at least one output MOSFET having an ESD resistant structure including a gate means without associated spacers, and means for electrically coupling the two together. The functional MOSFET includes a gate insulator, a conductive gate region over the gate insulator, spacers along the sidewalls of the gate insulator and conductive gate regions, a pair of LDD regions, and source/drain regions. The output MOSFET includes a gate insulator, a conductive gate region over the gate insulator, and source/drain regions. A further method for making an integrated circuit structure includes the step of creating a plurality of NMOS and PMOS gate structures including at least one NMOS gate structure for an ESD transistor. The method further includes making a PMOS LDD implant, making an NMOS LDD implant, creating spacers on the NMOS and PMOS gate structures, removing the spacers from the NMOS gate structure(s) for an ESD transistor, and making source/drain implants for the NMOS and PMOS gate structures.
Inventors
- 👤 Tiao-Yuan Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:18
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D89/00; H10D89/60; H10D89/601; H10D89/811
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
287 words
A method for making an integrated circuit structure comprising the steps of: fabricating at least one functional MOSFET over a semiconductor substrate including a lightly doped drain (LDD) region; fabricating at least one output MOSFET over said semiconductor substrate including a gate means without associated spacers; and electrically coupling said at least one functional MOSFET transistor to said at least one output MOSFET; wherein said step of fabricating at least one functional MOSFET comprises forming a gate structure over said semiconductor substrate, and said step of fabricating at least one output MOSFET comprises forming said gate means over said semiconductor substrate; and wherein the method further includes a step of simultaneously forming spacers along sidewalls of said gate structure of said at least one functional MOSFET and along sidewalls of said gate means of said at least one output MOSFET, and the method further includes a step of selectively removing the spacers from the sidewalls of said gate means of said at least one output MOSFET thereby to form said gate means of said at least one output MOSFET over said semiconductor substrate without associated spacers while said gate structure of said at least one functional MOSFET is left with the spacers at the sidewalls thereof after said step of selectively removing the spacers, and wherein the method further includes a step of implanting said semiconductor substrate with a dopant while said at least one functional MOSFET with said gate structure having spacers and said at least one output MOSFET with said gate means without associated spacers are both unmasked thereby to simultaneously form source and drain regions of said at least one functional MOSFET and of said at least one output MOSFET during said implanting step.
Claim 2
Independent Claim
287 words
A method for making an integrated circuit structure comprising the steps of: fabricating at least one functional MOSFET over a semiconductor substrate including a lightly doped drain (LDD) region; fabricating at least one output MOSFET over said semiconductor substrate including a gate means without associated spacers; and electrically coupling said at least one functional MOSFET transistor to said at least one output MOSFET; wherein said step of fabricating at least one functional MOSFET comprises forming a gate structure over said semiconductor substrate, and said step of fabricating at least one output MOSFET comprises forming said gate means over said semiconductor substrate; and wherein the method further includes a step of simultaneously forming spacers along sidewalls of said gate structure of said at least one functional MOSFET and along sidewalls of said gate means of said at least one output MOSFET, and the method further includes a step of selectively removing the spacers from the sidewalls of said gate means of said at least one output MOSFET thereby to form said gate means of said at least one output MOSFET over said semiconductor substrate without associated spacers while said gate structure of said at least one functional MOSFET is left with the spacers at the sidewalls thereof after said step of selectively removing the spacers, and wherein the method further includes a step of implanting said semiconductor substrate with a dopant while said at least one functional MOSFET with said gate structure having spacers and said at least one output MOSFET with said gate means without associated spacers are both unmasked thereby to simultaneously form source and drain regions of said at least one functional MOSFET and of said at least one output MOSFET during said implanting step.
Claim 3
Dependent Claim
60 words
A method for making an integrated circuit structure as recited in claim 1 wherein said step of fabricating at least one functional MOSFET further comprises: implanting said semiconductor substrate with a light dopant after said step of forming a gate structure and before said step of forming spacers along sidewalls of said gate structure thereby to form said LDD region.
Claim 4
Dependent Claim
58 words
A method for making an integrated circuit structure as recited in claim 2 wherein said step of implanting with a light dopant comprises implanting phosphorous into said semiconductor substrate at an energy in about a range of 40 to 150 keV and an implant density in about a range of 5×10 12 to 4×10 13 atoms/cm 2 .
Claim 5
Dependent Claim
53 words
A method for making an integrated circuit structure as recited in claim 1 wherein said step of implanting said semiconductor with a dopant comprises implanting arsenic into said semiconductor substrate at an energy in a range of 20 to 50 keV and an implant density of 1 to 5×10 15 atoms/cm 2 .
Claim 6
Dependent Claim
106 words
A method for making an integrated circuit structure as recited in claim 1 comprising: depositing a layer of insulating material over said semiconductor substrate; patterning said layer to simultaneously form said spacers along said sidewalls of said gate structure of said at least one functional MOSFET and to form spacers along sidewalls of said gate means of said at least one output MOSFET; and removing the spacers, by means of selective etching, from the sidewalls of said gate means of said at least one output MOSFET thereby to form said gate means of said at least one output MOSFET over said semiconductor substrate without associated spacers.
Claim 7
Dependent Claim
23 words
A method for making an integrated circuit structure as recited in claim 5 wherein said insulating material comprises silicon dioxide (SiO 2 ).
Claim 8
Dependent Claim
25 words
A method for making an integrated circuit structure as recited in claim 5 wherein said insulating material comprises silicon nitride (Si 3 N 4 ).
Claim 9
Dependent Claim
34 words
A method for making an integrated circuit structure as recited in claim 1 wherein said step of implanting said semiconductor substrate with a dopant forms said source and drain regions without a LDD region.
Claim 10
Dependent Claim
60 words
A method for making an integrated circuit structure as recited in claim 8 wherein said step of implanting to form said source and drain regions comprises implanting arsenic into said semiconductor substrate at an energy in about a range of 20 to 50 keV and an implant density in about a range of 1 to 5×10 15 atoms/cm 2 .
Claim 11
Dependent Claim
20 words
A method for making an integrated circuit structure as recited in claim 1 wherein said dopant is an n-type dopant.
Claim 12
Dependent Claim
20 words
A method for making an integrated circuit structure as recited in claim 1 wherein said dopant is an p-type dopant.
Claim 13
Independent Claim
187 words
A method for making an integrated circuit structure comprising the steps of: creating a plurality of NMOS and PMOS gate structures over a semiconductor substrate including at least one NMOS gate structure for an ESD transistor; making a LDD PMOS implant by forming LDD regions of p-type dopant in said semiconductor substrate under said PMOS gate structures; making a LDD NMOS implant by forming LDD regions of n-type dopant in said semiconductor substrate under said NMOS gate structures; creating spacers at sidewalls of said NMOS and PMOS gate structures; removing spacers from said at least one NMOS gate structure for an ESD transistor; and making source and drain implants of n-type dopant and of p-type dopant respectively for said NMOS and PMOS gate structures including said at least one NMOS gate structure for an ESD transistor, said making source and drain implants for said at least one NMOS gate structure for an ESD transistor being performed after said steps of creating spacers at sidewalls of said NMOS and PMOS gate structures and of removing spacers from said at least one NMOS gate structure for an ESD transistor.
Claim 14
Independent Claim
187 words
A method for making an integrated circuit structure comprising the steps of: creating a plurality of NMOS and PMOS gate structures over a semiconductor substrate including at least one NMOS gate structure for an ESD transistor; making a LDD PMOS implant by forming LDD regions of p-type dopant in said semiconductor substrate under said PMOS gate structures; making a LDD NMOS implant by forming LDD regions of n-type dopant in said semiconductor substrate under said NMOS gate structures; creating spacers at sidewalls of said NMOS and PMOS gate structures; removing spacers from said at least one NMOS gate structure for an ESD transistor; and making source and drain implants of n-type dopant and of p-type dopant respectively for said NMOS and PMOS gate structures including said at least one NMOS gate structure for an ESD transistor, said making source and drain implants for said at least one NMOS gate structure for an ESD transistor being performed after said steps of creating spacers at sidewalls of said NMOS and PMOS gate structures and of removing spacers from said at least one NMOS gate structure for an ESD transistor.
Claim 15
Dependent Claim
40 words
A method for making an integrated circuit structure as recited in claim 12 wherein said step of making a LDD PMOS implant comprises masking said NMOS gate structures, implanting said semiconductor substrate with said p-type dopant, and removing said masking.
Claim 16
Dependent Claim
52 words
A method for making an integrated circuit structure as recited in claim 12 wherein said step of making a LDD NMOS implant comprises masking said PMOS gate structures and said at least one NMOS gate structure for an ESD transistor, implanting said semiconductor substrate with said n-type dopant, and removing said masking.
Claim 17
Dependent Claim
46 words
A method for making an integrated circuit structure as recited in claim 12 wherein said step of creating spacers comprises depositing a layer of insulating material over said semiconductor substrate and said PMOS and NMOS gate structures, and patterning said insulating material to form said spacers.
Claim 18
Dependent Claim
56 words
A method for making an integrated circuit structure as recited in claim 15 wherein said step of removing spacers comprises masking said NMOS and PMOS gate structures without masking said at least one NMOS gate structure for an ESD transistor, and etching said spacers from said at least one NMOS gate structure for an ESD transistor.
Claim 19
Dependent Claim
38 words
A method for making an integrated circuit structure as recited in claim 12 wherein said step of making source/drain implants comprises masking said PMOS gate structures, implanting said semiconductor substrate with said n-type dopant, and removing said masking.
Claim 20
Dependent Claim
39 words
A method for making an integrated circuit structure as recited in claim 17 wherein said n-type dopant comprises arsenic implanted at an implant density of about 1-5×10 15 atoms/cm 2 and an energy of about 20 to 50 keV.
Claim 21
Dependent Claim
33 words
A method for making an integrated circuit structure as recited in claim 16 wherein said insulating material comprises silicon nitride, and wherein said etching step utilizes an etchant which preferentially removes silicon nitride.
Claim 22
Dependent Claim
20 words
A method for making an integrated circuit structure as recited in claim 15 wherein said insulating material comprises silicon dioxide.
Claim 23
Dependent Claim
41 words
A method for making an integrated circuit structure as recited in claim 14 wherein said n-type dopant comprises phosphorous implanted at an implant density of about 5×10 12 -4×10 13 atoms/cm 2 and an energy of about 40 to 150 keV.
Claim 24
Independent Claim
49 words
A method for making an integrated circuit structure as recited in 12 wherein said step of making source/drain implants comprises masking said NMOS gate structures and said at least one NMOS gate structure for an ESD transistor, implanting said semiconductor substrate with said p-type dopant, and removing said masking.
Claim 25
Independent Claim
49 words
A method for making an integrated circuit structure as recited in 12 wherein said step of making source/drain implants comprises masking said NMOS gate structures and said at least one NMOS gate structure for an ESD transistor, implanting said semiconductor substrate with said p-type dopant, and removing said masking.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-25 | 1999-12-25 | 2000-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-25 | 2003-12-25 | 2004-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-25 | 2007-12-25 | 2008-06-25 | $7700.00 | Window Closed / Lapsed |