System having multiple phase boosted charge pump with a plurality of stages

Claim 2

A computer system comprising: a central processing means; a memory means comprising memory elements and a charge pump for generating voltages for programming and erasing the memory elements; output display means; system busing means for transferring data and addresses between the central processing means, the main memory means, and the output display means; and an integrated circuit comprising: a charge pump circuit comprising a plurality of stages, each stage comprising a switching transistor device having gate, source and drain terminals, each switching transistor device of each stage being connected in series with the switching transistor devices of other stages of the plurality of stages, a control transistor device having gate, source and drain terminals, the drain and source terminals connecting the drain terminal and the gate terminal of the switching transistor device, and a storage capacitor joined to the source terminal of the switching transistor device; a source of voltage to be pumped and coupled to the drain terminal of the switching transistor device of a first stage; a source of a first series of clock pulses; circuitry connecting the first series of clock pulses to the gate terminals of the switching transistor devices in odd stages of the charge pump and to the gate terminals of the control transistor devices in even stages; a source of a second series of clock pulses which do not overlap the first series of clock pulses; and circuitry connecting the second series of clock pulses to the gate terminals of the switching transistor devices which do not receive the first series of clock pulses and to the gate terminals of the control transistor devices which do not receive the first series of clock pulses such that the switching transistor devices are switched on by a higher gate voltage than drain voltage to charge the next stage of the charge pump.

Claim 3

A computer system as claimed in claim 1, wherein the control transistor device has a gate, source and drain terminals, and the gate of the control transistor device is connected to the source terminal of the switching transistor device.

Claim 4

A computer system comprising: a central processing means; a memory means comprising memory elements and a charge pump for generating voltages for programming and erasing the memory elements; output display means; system busing means for transferring data and addresses between the central processing means, the main memory means, and the output display means; and an integrated circuit comprising: a charge pump circuit comprising: a plurality of stages, each stage comprising: a switching transistor device having gate, source, and drain terminals, each switching transistor device corresponding to a stage being connected in series with the switching transistor devices of other stages, means for connecting the drain terminal and the gate terminal of the switching transistor device, and storage means joined to the source terminal of the switching device; means for providing a voltage to be pumped at the drain terminal of the switching transistor device of a first stage of the charge pump circuit; means for furnishing a first set of clock pulses; means for furnishing a second set of clock pulses which do not overlap the first set of clock pulses; means for applying pulses of the first series of clock pulses to the gate terminals of the switching transistor devices in odd stages of the charge pump circuit and to the gate terminals of the control transistor devices in even stages of the charge pump; means for applying pulses of the second series of clock pulses to the gate terminals of the switching transistor devices which do not receive the first series of clock pulses and to the gate terminal of the control transistor devices which do not receive the first series of clock pulses; means responsive to the first and second series of clock pulses for disabling the means for connecting the drain terminal and the gate terminal of the switching transistor device of each stage of the charge pump circuit during a period beginning when the switching transistor of a corresponding stage is turned on and continuing until the storage means of the stage has charged to a voltage level equal to a voltage level at the drain of the switching transistor device of the stage, whereby the gate of the switching transistor device of each stage is held at a voltage level during conduction sufficient to eliminate threshold voltage drop.

Claim 5

A computer system comprising: a central processing means; a memory means comprising memory elements and a charge pump for generating voltages for programming and erasing the memory elements; output display means; system busing means for transferring data and addresses between the central processing means, the main memory means, and the output display means; and an integrated circuit comprising: a charge pump circuit comprising: a plurality of stages, each stage comprising: a switching transistor device having gate, source, and drain terminals, each switching transistor device corresponding to a stage being connected in series with the switching transistor devices of other stages, means for connecting the drain terminal and the gate terminal of the switching transistor device, and storage means joined to the source terminal of the switching device; means for providing a voltage to be pumped at the drain terminal of the switching transistor device of a first stage of the charge pump circuit; means for furnishing a first set of clock pulses; means for furnishing a second set of clock pulses which do not overlap the first set of clock pulses; means for applying pulses of the first series of clock pulses to the gate terminals of the switching transistor devices in odd stages of the charge pump circuit and to the gate terminals of the control transistor devices in even stages of the charge pump; means for applying pulses of the second series of clock pulses to the gate terminals of the switching transistor devices which do not receive the first series of clock pulses and to the gate terminal of the control transistor devices which do not receive the first series of clock pulses; means responsive to the first and second series of clock pulses for disabling the means for connecting the drain terminal and the gate terminal of the switching transistor device of each stage of the charge pump circuit during a period beginning when the switching transistor of a corresponding stage is turned on and continuing until the storage means of the stage has charged to a voltage level equal to a voltage level at the drain of the switching transistor device of the stage, whereby the gate of the switching transistor device of each stage is held at a voltage level during conduction sufficient to eliminate threshold voltage drop.

Claim 6

A computer system as claimed in claim 3 further comprising an output stage comprising a switching transistor device having gate, source and drain terminals, the source and drain terminals being connected in series with the source and drain terminals of the switching transistor devices of all other stages, and the gate terminal being connected to the drain terminal.

Claim 7

A computer system as claimed in claim 3 in which the means for connecting the drain terminal and the gate terminal of the switching transistor device comprises a control transistor device having gate, source, and drain terminals, the source and drain terminals being connected in a path between the gate and drain terminals of the switching transistor device of that stage.

Claim 8

A computer system as claimed in claim 5 in which the means responsive to the first and second series of clock pulses for disabling the means for connecting the drain terminal and the gate terminal of the switching transistor device of each stage of the charge pump circuit during a period beginning when the switching transistor of a corresponding stage is turned on and continuing until the storage means of the corresponding stage has charged to a voltage level equal to a voltage level at the drain of the switching transistor device of the stage, comprises: means for furnishing the first set of clock pulses to the gate terminals of the control transistor devices in stages in which the second set of clock pulses is applied to the gate of the switching transistor device, and means for furnishing the second set of clock pulses to the gate terminals of the control transistor devices in stages in which the first set of clock pulses is applied to the gate of the switching transistor device.

Claim 9

A computer system as claimed in claim 6 in which the storage means joined to the source terminal of the switching device comprises a capacitor, in which the means for furnishing the first set of clock pulses to the gate terminals of control transistor devices in stages in which the second set of clock pulses is applied to the gate of the switching transistor device, comprises means furnishing the first set of clock pulses to the capacitor and means joining the capacitor to the gate terminal of the control transistor device of that stage; and in which the means for furnishing the second set of clock pulses to the gate terminals of control transistor devices in stages in which the first set of clock pulses is applied to the gate of the switching transistor device comprises means furnishing the second set of clock pulses to the capacitor and means joining the capacitor to the gate terminal of the control transistor device of that stage.

Claim 10

A computer system as claimed in claim 7 in which each of the switching transistor devices and each of the control transistor devices is an S type field effect transistor device.

Claim 11

A computer system as claimed in claim 5, wherein the control transistor device has gate, source, and drain terminals, and the gate of the control transistor device is connected to the source terminal of the switching transistor device.