US5524092A
Expired / Lapsed
US
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Multilayered ferroelectric-semiconductor memory-device
Assignee: Individual
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Filing: 1995-02-17
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Granted: 1996-06-04
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Expires: 2015-02-17
Abstract
Abstract Disclosed is a novel ferroelectric-semiconductor interface memory element for a dual-valued, capacitive memory diode of an integrated circuit which consists of a layer of metal electrode, a layer of diffusion barrier conductor, a layer of ferroelectric material, a layer of semiconductor crystal, and a layer of metal electrode. Also disclosed is an alternative, novel, ferroelectric-semiconductor interface memory element for a dual-valued, capacitive memory diode of an integrated circuit which consists of a layer of metal electrode, a layer of diffusion barrier conductor, a layer of ferroelectric material, another layer of diffusion barrier conductor, a layer of semiconductor crystal, and a layer of metal electrode. The two values of maximum capacitance in a single capacitor are achieved in these capacitive diodes by making use of accumulation, depletion, or inversion of semiconductor surface charges as a result of the orientation of the remnant polarization of ferroelectric in proximity.
Inventors
- 👤 Jea K. Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:04
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/682; G; G11; G11C; G11C11/00; G11C11/56; G11C11/5657; H10D1/692
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
136 words
A multilayered ferroelectric-semiconductor and dual-valued capacitive memory-device comprising: a first layer comprising a metal or a heavily doped polysilicon electrode layer; a second layer comprising a diffusion barrier conductor and an adhesion promoter out of refractory metal or conducting oxide; a third layer comprising a ferroelectric thin film; a fourth layer comprising a semiconductor crystal layer or a semiconductor crystal substrate; a fifth layer comprising a metal electrode; wherein said first layer is in direct contact with said second layer, said second lawyer is in direct contact with said third layer, said third layer is in direct contact with said fourth layer, and said fourth layer is in direct contact with said fifth layer, and wherein said first layer to said fifth layer are arranged in the order from a top layer to a bottom layer.
Claim 2
Dependent Claim
136 words
A multilayered ferroelectric-semiconductor and dual-valued capacitive memory-device comprising: a first layer comprising a metal or a heavily doped polysilicon electrode layer; a second layer comprising a diffusion barrier conductor and an adhesion promoter out of refractory metal or conducting oxide; a third layer comprising a ferroelectric thin film; a fourth layer comprising a semiconductor crystal layer or a semiconductor crystal substrate; a fifth layer comprising a metal electrode; wherein said first layer is in direct contact with said second layer, said second lawyer is in direct contact with said third layer, said third layer is in direct contact with said fourth layer, and said fourth layer is in direct contact with said fifth layer, and wherein said first layer to said fifth layer are arranged in the order from a top layer to a bottom layer.
Claim 3
Dependent Claim
28 words
A device of claim 1, wherein a first electrode of the multilayered ferroelectric-semiconductor and dual-valued capacitive memory-device comprises a combination of said first layer and said second layer.
Claim 4
Dependent Claim
54 words
A device of claim 1, wherein said first layer of the multilayered ferroelectric-semiconductor and dual-valued capacitive memory-device comprises a conductor from a high conductivity metal, such as aluminum(Al), gold(Au) or platinum(Pt), or a heavily doped polysilicon electrode layer with a thickness from about 1000 Å to 10,000 Å depending upon a required conductance value.
Claim 5
Dependent Claim
54 words
A device of claim 1, wherein said second layer of the multilayered ferroelectric-semiconductor and dual-valued capacitive memory-device comprises the diffusion barrier conductor and the adhesion promoter in one layer from the refractory metal, the conducting oxide, or a conducting silicon-nitride with a thickness not exceeding 1000 Å in order to have a proximity effect.
Claim 6
Dependent Claim
54 words
A device of claim 1, wherein said third layer of the multilayered ferroelectric-semiconductor and dual-valued capacitive memory-device comprises a spontaneously polarizable ferroelectric material for the ferroelectric thin film from barium titanate(BaTiO 3 ), lead zirconate titanate(PZT), or lanthanium doped lead zirconate titanate(PLXT) with a thickness not exceeding 10,000 Å for a planar device application.
Claim 7
Dependent Claim
35 words
A device of claim 1, wherein said fourth layer of the multilayered ferroelectric-semi-conductor and dual-valued capacitive memory-device comprises the semiconductor crystal layer with a thickness exceeding 1000 Å in order to have practical capacitance values.
Claim 8
Dependent Claim
43 words
A device of claim 2, wherein said fifth layer of the multilayered ferroelectric-semiconductor and dual-valued capacitive memory-device, which is also a second electrode, comprises a metal to semiconductor ohmic contact as the metal electrode to said fourth layer of the semiconductor crystal substrate.
Claim 9
Dependent Claim
169 words
A multilayered ferroelectric-semiconductor and dual-valued capacitive memory-device comprising: a first layer comprising a metal or a heavily doped polysilicon electrode layers a second layer comprising a diffusion barrier conductor and an adhesion promoter out of refractory metal or conducting oxide; a third layer comprising a ferroelectric than film; a fourth layer comprising a diffusion barrier conductor and an adhesion promoter out of refractory metal, or conducting oxide such as indium-tin-oxide; a fifth layer comprising a semiconductor crystal layer, or a semiconductor crystal substrate; a sixth layer comprising a metal electrode; wherein said first layer is in direct contact with said second layer, said second layer is in direct contact with said third layer, said third layer is in direct contact with said fourth layer, said fourth layer is in direct contact with said fifth layer, and said fifth layer is in direct contact with said sixth layer, and wherein said first layer to said sixth layer are arranged in the order from a top layer to a bottom layer.
Claim 10
Dependent Claim
169 words
A multilayered ferroelectric-semiconductor and dual-valued capacitive memory-device comprising: a first layer comprising a metal or a heavily doped polysilicon electrode layers a second layer comprising a diffusion barrier conductor and an adhesion promoter out of refractory metal or conducting oxide; a third layer comprising a ferroelectric than film; a fourth layer comprising a diffusion barrier conductor and an adhesion promoter out of refractory metal, or conducting oxide such as indium-tin-oxide; a fifth layer comprising a semiconductor crystal layer, or a semiconductor crystal substrate; a sixth layer comprising a metal electrode; wherein said first layer is in direct contact with said second layer, said second layer is in direct contact with said third layer, said third layer is in direct contact with said fourth layer, said fourth layer is in direct contact with said fifth layer, and said fifth layer is in direct contact with said sixth layer, and wherein said first layer to said sixth layer are arranged in the order from a top layer to a bottom layer.
Claim 11
Dependent Claim
28 words
A device of claim 8, wherein a first electrode of the multilayered ferroelectric-semiconductor and dual-valued capacitive memory-device comprises a combination of said first layer and said second layer.
Claim 12
Dependent Claim
54 words
A device of claim 8, wherein said first layer of the multilayered ferroelectric-semiconductor and dual-valued capacitive memory-device comprises a conductor from a high conductivity metal, such as aluminum(Al), gold(Au) or platinum(Pt), or a heavily doped polysilicon electrode layer with a thickness from about 1000 Å to 10,000 Å depending upon a required conductance value.
Claim 13
Dependent Claim
54 words
A device of claim 8, wherein said second layer of the multilayered ferroelectric-semiconductor and dual-valued capacitive memory-device comprises the diffusion barrier conductor and the adhesion promoter in one layer from the refractory metal, the conducting oxide, or a conducting silicon-nitride with a thickness not exceeding 1000 Å in order to have a proximity effect.
Claim 14
Dependent Claim
54 words
A device of claim 8, wherein said third layer of the multilayered ferroelectric-semiconductor and dual-valued capacitive memory-device comprises a spontaneously polarizable ferroelectric material for the ferroelectric thin film from barium titanate(BaTiO 3 ), lead zirconate titanate(PZT), or lanthanium doped lead zirconate titanate(PLZT) with a thickness not exceeding 10,000 Å for a planar device application.
Claim 15
Dependent Claim
54 words
A device of claim 8, wherein said fourth layer of the multilayered ferroelectric-semiconductor and dual-valued capacitive memory-device comprises the diffusion barrier conductor and the adhesion promoter in one layer from, the refractory metal, the conducting oxide, or a conducting nitride with a thickness not exceeding 1000 Å in order to have a proximity effect.
Claim 16
Dependent Claim
34 words
A device of claim 8, wherein said fifth layer of the multilayered ferroelectric-semiconductor and dual-valued capacitive memory-device comprises the semiconductor crystal layer with a thickness exceeding 10,000 Å in order to be a substrate.
Claim 17
Dependent Claim
42 words
A device of claim 9, wherein said sixth layer of the multilayered ferroelectric-semiconductor and dual-valued capacitive memory-device, which is also second electrode, comprises a metal to semiconductor ohmic contact as the metal electrode to said fifth layer of the semiconductor crystal substrate.
References Cited (Backward Citations)
US3728694A
Cited
US5024964A
Cited
US5375082A
Cited
US5331187A
Cited
US5390142A
Cited
US5341325A
Cited
US5416042A
Cited
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