Data processing apparatus for dynamically setting timings in a dynamic memory system

Claim 1

A data processing system comprising: a dynamic read/write memory including a plurality of memory modules each having a plurality of addressable storage locations; a single memory controller for controlling operation of all of said memory modules; a processor for initiating memory access cycles to read data from said memory and write data into said memory, said processor being operable to selectively produce accessing signals including cycle definition and address signals to start a memory access cycle; and bus means interconnecting said processor, said memory, and said memory controller to transfer data and accessing signals therebetween; each memory module being accessible in response to receiving module operating signals including read/write, row address, column address, row address strobe (RAS), and column address strobe (CAS) signals; said memory controller being operable to transmit said module operating signals to a memory module, in response to receiving accessing signals from said processor, said memory controller comprising timing means including a clock input line for receiving system clock signals and operating said memory controller at the speed of said system clock signals; a plurality of programmable definition registers each associated with a different one of said memory modules, each definition register being operative to store pulse control signals specific to the timing requirements of the associated memory module, said pulse control signals in each definition register specifying said timing requirements as integral numbers of said clock periods, a sequencer connected to said memory modules for generating said module operating signals; and means, responsive to said address signals, for gating said pulse control signals from the definition register associated with the memory module being addressed, to said sequencer, said sequencer being operative to set the timing of said module operating signals in accordance with the timing requirements specified by said pulse control signals.