US5522046A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Communication system uses diagnostic processors and master processor module to identify faults and generate mapping tables to reconfigure communication paths in a multistage interconnect network
Assignee: Teradata US Inc
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Filing: 1994-06-03
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Granted: 1996-05-28
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Expires: 2014-06-03
Abstract
Abstract A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 log b N stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and log b N indicates a ceiling function providing the smallest integer not less than log b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
Inventors
- 👤 Robert J. McMillen
- 👤 M. Cameron Watson
- 👤 David J. Chura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:05
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/20; G06F11/2002; G06F11/2005; G01; G01J; G01J3/00; G01J3/02; G01J3/06; G06F11/14; G06F11/1402; G06F11/1415; G06F11/142; G06F11/1423; G06F11/22; H; H04; H04L; H04L49/00; H04L49/15; H04L49/1515; H04L49/35; H04L49/356; H04L49/358; H04L49/55; H04L49/552; H04L49/555; H04L49/557; H04Q; H04Q3/00; H04Q3/64; H04Q3/68; G06F11/2007; G06F2201/00; G06F2201/85; H04Q2213/00; H04Q2213/13332
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
167 words
A communications system, comprising: a multistage interconnect network comprising a plurality of interconnected active logic switch nodes, each of the switch nodes further comprising means for detecting faults in the switch node, and means for storing a mapping table in the switch node that identifies active and inactive communications ports of the switch node; one or more diagnostic processors, coupled to each of the switch nodes, for receiving data from each of the switch nodes identifying the detected faults in each of the switch nodes, and for transmitting the mapping tables to the switch nodes; and a master processor module, coupled to the diagnostic processors, for receiving the data from the diagnostic processors identifying the detected faults in the switch nodes, for generating the mapping tables to activate and deactivate communications ports in each of the switch nodes based on the received data to thereby re-configure communications paths between switch nodes, and for transmitting the mapping tables to the diagnostic processor for storage into the switch nodes.
Claim 2
Dependent Claim
167 words
A communications system, comprising: a multistage interconnect network comprising a plurality of interconnected active logic switch nodes, each of the switch nodes further comprising means for detecting faults in the switch node, and means for storing a mapping table in the switch node that identifies active and inactive communications ports of the switch node; one or more diagnostic processors, coupled to each of the switch nodes, for receiving data from each of the switch nodes identifying the detected faults in each of the switch nodes, and for transmitting the mapping tables to the switch nodes; and a master processor module, coupled to the diagnostic processors, for receiving the data from the diagnostic processors identifying the detected faults in the switch nodes, for generating the mapping tables to activate and deactivate communications ports in each of the switch nodes based on the received data to thereby re-configure communications paths between switch nodes, and for transmitting the mapping tables to the diagnostic processor for storage into the switch nodes.
Claim 3
Dependent Claim
67 words
The system of claim 1, wherein each switch node further comprises means for disabling the communication ports according to input/output enable vectors, and the master processor module further comprises means for generating the input/output enable vectors from the received data and means for transmitting the enable vectors to the switch nodes via the diagnostic processor to configure the communications paths around faulty switch nodes in the network.
Claim 4
Dependent Claim
31 words
The system of claim 2, wherein the master processor module processor further comprises means for initializing the network during startup by configuring the communication paths between switch nodes in the network.
Claim 5
Dependent Claim
13 words
The system of claim 3, further comprising redundant networks for added fault tolerance.
Claim 6
Dependent Claim
17 words
The system of claim 4, further comprising control means for load leveling communications through the redundant networks.
Claim 7
Dependent Claim
36 words
The system of claim 5, further comprising control means for switching between redundant networks when a failure occurs, so that if one or more of the redundant networks is not available, the others can take over.
Claim 8
Dependent Claim
30 words
The system of claim 1, wherein the diagnostic processor further comprises a means for commanding a self-test from a selected switch node to thereby identify faults within the switch node.
Claim 9
Dependent Claim
234 words
A multiprocessor system, comprising: a plurality of processors; a network interconnecting the processors, comprising a plurality of logic switch nodes having input/output ports, each of the switch nodes further comprising means for detecting faults in the switch node, and means for storing a mapping table in the switch node that identifies active and inactive input/output ports of the switch node, the switch nodes arranged into more than log b N switch node stages, wherein b is a total number of switch node input/output ports, and log b N indicates a ceiling function providing the smallest integer not less than log b N, the switch node stages thereby providing a plurality of paths between any network input port and network output port; one or more diagnostic processors, coupled to each of the switch nodes, for receiving data from each of the switch nodes identifying the detected faults in each of the switch nodes, and for transmitting the mapping tables to the switch nodes; and a master processor module, coupled to the diagnostic processors, for receiving the data from the diagnostic processors identifying the detected faults in the switch nodes, for generating the mapping tables to activate and deactivate communications ports in each of the switch nodes based on the received data to thereby re-configure communications paths between switch nodes, and for transmitting the mapping tables to the diagnostic processor for storage into the switch nodes.
Claim 10
Dependent Claim
234 words
A multiprocessor system, comprising: a plurality of processors; a network interconnecting the processors, comprising a plurality of logic switch nodes having input/output ports, each of the switch nodes further comprising means for detecting faults in the switch node, and means for storing a mapping table in the switch node that identifies active and inactive input/output ports of the switch node, the switch nodes arranged into more than log b N switch node stages, wherein b is a total number of switch node input/output ports, and log b N indicates a ceiling function providing the smallest integer not less than log b N, the switch node stages thereby providing a plurality of paths between any network input port and network output port; one or more diagnostic processors, coupled to each of the switch nodes, for receiving data from each of the switch nodes identifying the detected faults in each of the switch nodes, and for transmitting the mapping tables to the switch nodes; and a master processor module, coupled to the diagnostic processors, for receiving the data from the diagnostic processors identifying the detected faults in the switch nodes, for generating the mapping tables to activate and deactivate communications ports in each of the switch nodes based on the received data to thereby re-configure communications paths between switch nodes, and for transmitting the mapping tables to the diagnostic processor for storage into the switch nodes.
Claim 11
Dependent Claim
32 words
The system of claim 8, wherein the master processor module further comprises means for disabling one or more communications ports to re-configure the communications paths around faulty switch nodes in the network.
Claim 12
Dependent Claim
73 words
The system of claim 9, wherein the means for disabling further comprises: means for tracing back on all input ports of a faulty switch node to switch nodes connected thereto and means for disabling corresponding output ports of each connected switch node; and means for tracing forward on all output ports of a faulty switch node to switch nodes connected thereto and means for disabling corresponding input ports of each connected switch node.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-28 | 1999-11-27 | 2000-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-28 | 2003-11-27 | 2004-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-28 | 2007-11-27 | 2008-05-28 | $7700.00 | Window Closed / Lapsed |