Speed independent arbiter switch employing M-out-of-N codes

Claim 2

An arbiter comprised of: two input ports and one output port, each of said input ports having N input data lines and said one output port having N output data lines; means for selecting only one of said two input ports at a time in response to an active logic signal on any one of the N input data lines in that port when neither input port is already selected; and means for passing the bits of multibit characters from said selected input port to said output port in parallel and in synchronization with each other; each of said multibit characters being represented by active logic signals that asynchronously occur with respect to each other on M-out-of-N data lines on said selected input port, with M being at least two and N being greater than M and greater than three.

Claim 3

An arbiter according to claim 1 wherein said means for passing includes an N-bit wide queue means for receiving characters from said selected input port and for transmitting said received characters to said output port.

Claim 4

An arbiter according to claim 1 wherein each of said input ports further includes one input control line, and wherein said means for passing includes means for generating control signals on said one input control line of said selected input port indicating when characters on the N input data lines of said selected input port are accepted and can change.

Claim 5

An arbiter according to claim 1 wherein said output port further includes one output control line, and wherein said means for passing includes means for generating characters on said N output data lines of said output port in response to signals on said one output control line.

Claim 6

An arbiter according to claim 1 and further including means for detecting a predetermined character on said N input data lines of said selected input port and in response thereto for generating one of two characters on said N output data lines of said output port indicating which input port is selected.

Claim 7

An arbiter according to claim 1 and further including means for detecting a predetermined character on said N input data lines of said selected input port and in response thereto for deselecting from said selected input port.

Claim 8

An arbiter comprised of: two input port means and one output port means; each of said input port means including N input data lines for receiving sequences of externally generated multibit characters of the form A S . . . A S M . . . MC EM A A . . . A A C EA , said characters A S , M, C EM , A A and C EA being represented by active logic signals that asynchronously occur with respect to each other on M-out-of-N of said N input data lines with M being at least two and N being greater than M and greater than three; said output port means having N output data lines and including: means for passing the multiple bits of the respective characters from either of said two input port means to said one output port means in parallel and in synchronization with each other, and means for generating one of two selectable characters on said output port immediately after said C EM character is passed thereto to identify the input port that said character sequence is being passed from.

Claim 9

An arbiter comprised of: two input port means and one output port means; each of said input port means including N input data lines for receiving sequences of externally generated multibit characters of the form A S . . . A S M . . . MC EM A A . . . A A C EA , said characters A S , M, C EM , A A and C EA being represented by active logic signals that asynchronously occur with respect to each other on M-out-of-N of said N input data lines with M being at least two and N being greater than M and greater than three; said output port means having N output data lines and including: means for passing the multiple bits of the respective characters from either of said two input port means to said one output port means in parallel and in synchronization with each other, and means for generating one of two selectable characters on said output port immediately after said C EM character is passed thereto to identify the input port that said character sequence is being passed from.

Claim 10

An arbiter comprised of: two input ports and one output port, each of said input ports having N input data lines and said one output port having N output data lines; means for selecting only one of said two input ports at a time; and means for passing the bits of multibit characters from said selected input port to said output port including an N-bit wide queue means for asynchronously receiving the bits of each character from said selected input port and for transmitting the received bits of each character in parallel and in synchronization with each other to said output port; each of said multibit characters being represented by active logic signals that asynchronously occur with respect to each other on M-out-of-N data lines on said selected input port, with M being at least two and N being greater than M and greater than three.

Claim 11

An arbiter comprised of: two input ports and one output port, each of said input ports having N input data lines and said one output port having N output data lines; means for selecting only one of said two input ports at a time; and means for passing the bits of multibit characters from said selected input port to said output port including an N-bit wide queue means for asynchronously receiving the bits of each character from said selected input port and for transmitting the received bits of each character in parallel and in synchronization with each other to said output port; each of said multibit characters being represented by active logic signals that asynchronously occur with respect to each other on M-out-of-N data lines on said selected input port, with M being at least two and N being greater than M and greater than three.

Claim 12

An arbiter comprised of: two input ports and one output port, each of said input ports having N input data lines and said one output port having N output data lines; means for selecting only one of said two input ports at a time; and means for passing the bits of multibit characters from said selected input port to said output port in parallel and in synchronization with each other; each of said multibit characters being represented by active logic signals that asynchronously occur with respect to each other on M-out-of-N data line on said selected input port, with M being at least two and N being greater than M and greater than three; each of said input ports further including one input control line, and said means for passing including means for generating control signals on said one input control line of said selected input port indicating when the asynchronous bits of each character on the N input data lines of said selected input port are accepted and can change.

Claim 13

An arbiter comprised of: two input ports and one output port, each of said input ports having N input data lines and said one output port having N output data lines; means for selecting only one of said two input ports at a time; and means for passing the bits of multibit characters from said selected input port to said output port in parallel and in synchronization with each other; each of said multibit characters being represented by active logic signals that asynchronously occur with respect to each other on M-out-of-N data line on said selected input port, with M being at least two and N being greater than M and greater than three; each of said input ports further including one input control line, and said means for passing including means for generating control signals on said one input control line of said selected input port indicating when the asynchronous bits of each character on the N input data lines of said selected input port are accepted and can change.