Semiconductor memory device having cell isolation structure

Claim 2

A semiconductor memory device comprising: a semiconductor substrate; a plurality of first element separation oxide films formed on a surface of said semiconductor substrate, said plurality of first element separation oxide films being arranged in lines parallel to each other; first and second memory cells formed in said semiconductor substrate between adjacent ones of said first element separation oxide films; and a second element separation oxide film formed on the surface of said semiconductor substrate between said first and second memory cells, said second element separation oxide film having a thickness less than a thickness of said first element separation oxide films.

Claim 3

A semiconductor memory device according to claim 1, wherein each of said first and second memory cells have a transistor and a capacitor connected to a current path of said transistor, said transistor including a gate insulated from said semiconductor substrate by a gate insulating film formed on said semiconductor substrate anti source and drain regions formed in said semiconductor substrate, said capacitor being formed in a trench in said semiconductor substrate.

Claim 4

A semiconductor memory device comprising: a semiconductor substrate; a plurality of first element separation oxide films formed on a surface of said semiconductor substrate, said plurality of first element separation oxide films being arranged in lines parallel to each other; first and second memory cells formed in said semiconductor substrate between adjacent ones of said first element separation oxide films, each of said first and second memory cells having a transistor and a capacitor connected to a current path of said transistor, said transistor including a gate insulated from said semiconductor substrate by a gate insulating film formed on said semiconductor substrate and source and drain regions formed in said semiconductor substrate, and said capacitor being formed in a trench in said semiconductor substrate; an insulating layer formed on said capacitor; a pass word line formed on said insulating layer; and a second element separation oxide film formed on a portion of said surface of said semiconductor substrate located between said first and second memory cells, a thickness of said second element separation oxide film being less than a thickness of said first element separation oxide films.

Claim 5

A semiconductor memory device comprising: a semiconductor substrate; a plurality of first element separation oxide films formed on a surface of said semiconductor substrate, said plurality of first element separation oxide films being arranged in lines parallel to each other; first and second memory cells formed in said semiconductor substrate between adjacent ones of said first element separation oxide films, each of said first and second memory cells having a transistor and a capacitor connected to a current path of said transistor, said transistor including a gate insulated from said semiconductor substrate by a gate insulating film formed on said semiconductor substrate and source and drain regions formed in said semiconductor substrate, and said capacitor being formed in a trench in said semiconductor substrate; an insulating layer formed on said capacitor; a pass word line formed on said insulating layer; and a second element separation oxide film formed on a portion of said surface of said semiconductor substrate located between said first and second memory cells, a thickness of said second element separation oxide film being less than a thickness of said first element separation oxide films.

Claim 6

A semiconductor memory device according to claim 3, wherein said capacitor comprises a sheath plate capacitor.

Claim 7

A semiconductor memory device according to claim 4, wherein said sheath plate capacitor comprises: a plate electrode formed in said trench; a storage node formed in said plate electrode and connected to a current path of said transistor; and an insulating film formed between said plate electrode and said storage node.

Claim 8

A semiconductor memory device comprising: a semiconductor substrate; a plurality of first element separation oxide films formed on a surface of said semiconductor substrate, said plurality of first element separation oxide films being arranged in lines parallel to each other; first and second memory cells formed on said semiconductor substrate between adjacent ones of said first element separation oxide films, each of said first and second memory cells having a transistor and a capacitor; a second element separation oxide film formed on a portion of said surface of said semiconductor substrate located between said first and second memory cells, a thicknesses of said second element separation oxide film being less than a thickness of said first element separation oxide films; and a pass word line formed on said second element separation oxide film.

Claim 9

A semiconductor memory device comprising: a semiconductor substrate; a plurality of first element separation oxide films formed on a surface of said semiconductor substrate, said plurality of first element separation oxide films being arranged in lines parallel to each other; first and second memory cells formed on said semiconductor substrate between adjacent ones of said first element separation oxide films, each of said first and second memory cells having a transistor and a capacitor; a second element separation oxide film formed on a portion of said surface of said semiconductor substrate located between said first and second memory cells, a thicknesses of said second element separation oxide film being less than a thickness of said first element separation oxide films; and a pass word line formed on said second element separation oxide film.

Claim 10

A semiconductor memory device according to claim 6, wherein said capacitor comprises a stacked capacitor.

Claim 11

A semiconductor memory device according to claim 7, wherein said stacked capacitor comprises: a storage node formed on said semiconductor substrate and connected to a current path of said transistor; and a plate electrode formed above said storage node, said plate electrode being insulated from said storage node by an insulating layer.

Claim 12

A semiconductor memory device comprising: a semiconductor substrate; first, second and third element separation oxide films formed on a surface of said semiconductor substrate, said first, second and third element separation oxide films being arranged in lines parallel to each other; first and second memory cells formed in said semiconductor substrate between said first and second element separation oxide films, each of said first and second memory cells having a first transistor and a first capacitor connected to a current path of said first transistor, said first transistor including a first gate insulated from said semiconductor substrate by a gate insulating film formed on said semiconductor substrate and source and drain regions formed in said semiconductor substrate, and said first capacitor formed in a first trench in said semiconductor substrate; third and fourth memory cells formed in said semiconductor substrate between said second and third element separation oxide films and being shifted in a direction parallel to said first, second, and third element separation oxide films from said first and second memory cells, each of said third and fourth memory cells having a second transistor including a second gate as a word line and a second capacitor connected to a current path of said second transistor, said word line extending above said first capacitor of one of said first and second memory cells, said second capacitor formed in a second trench in said semiconductor substrate; and a plurality of fourth element separation oxide films formed on a portion of said surface of said semiconductor substrate, at least one first fourth element separation oxide film located between said first trenches of said first and second memory cells and at least one second fourth element separation oxide film located between said second trenches of said third and fourth memory cells, a thickness of said fourth element separation oxide films being less than a thickness of said first, second, and third element separation oxide films.

Claim 13

A semiconductor memory device comprising: a semiconductor substrate; first, second and third element separation oxide films formed on a surface of said semiconductor substrate, said first, second and third element separation oxide films being arranged in lines parallel to each other; first and second memory cells formed in said semiconductor substrate between said first and second element separation oxide films, each of said first and second memory cells having a first transistor and a first capacitor connected to a current path of said first transistor, said first transistor including a first gate insulated from said semiconductor substrate by a gate insulating film formed on said semiconductor substrate and source and drain regions formed in said semiconductor substrate, and said first capacitor formed in a first trench in said semiconductor substrate; third and fourth memory cells formed in said semiconductor substrate between said second and third element separation oxide films and being shifted in a direction parallel to said first, second, and third element separation oxide films from said first and second memory cells, each of said third and fourth memory cells having a second transistor including a second gate as a word line and a second capacitor connected to a current path of said second transistor, said word line extending above said first capacitor of one of said first and second memory cells, said second capacitor formed in a second trench in said semiconductor substrate; and a plurality of fourth element separation oxide films formed on a portion of said surface of said semiconductor substrate, at least one first fourth element separation oxide film located between said first trenches of said first and second memory cells and at least one second fourth element separation oxide film located between said second trenches of said third and fourth memory cells, a thickness of said fourth element separation oxide films being less than a thickness of said first, second, and third element separation oxide films.

Claim 14

A semiconductor memory device according to claim 9, wherein each of said first and second capacitors comprises a sheath plate capacitor.

Claim 15

A semiconductor memory device according to claim 10, wherein each of said sheath plate capacitor comprises: a plate electrode formed in said respective first or second trench; a storage node formed in said plate electrode and connected to the current path of said respective first or second transistor; and an insulating film formed between said plate electrode and said storage node.

Claim 16

A semiconductor memory device according to claim 9, wherein a position of said third and fourth memory cells is shifted at a half pitch from said first and second memory cells, respectively.

Claim 17

A semiconductor memory device, comprising: a semiconductor substrate; a plurality of parallel insulative strips formed on a major surface of said semiconductor substrate, said parallel insulative strips extending in a first direction on said major surface and having spacings therebetween; a first memory cell pair comprising first and second memory cells formed in the spacing between first and second ones of said parallel insulative strips; and an insulating film formed on the major surface of said semiconductor substrate between the first and second ones of said parallel insulative strips and between the first and second memory cells of said first memory cell pair, wherein the thickness of said insulating film is less than the thickness of said parallel insulative strips.

Claim 18

A semiconductor memory device, comprising: a semiconductor substrate; a plurality of parallel insulative strips formed on a major surface of said semiconductor substrate, said parallel insulative strips extending in a first direction on said major surface and having spacings therebetween; a first memory cell pair comprising first and second memory cells formed in the spacing between first and second ones of said parallel insulative strips; and an insulating film formed on the major surface of said semiconductor substrate between the first and second ones of said parallel insulative strips and between the first and second memory cells of said first memory cell pair, wherein the thickness of said insulating film is less than the thickness of said parallel insulative strips.

Claim 19

A semiconductor memory device according to claim 13, wherein each of said first and second memory cells has a transistor and a capacitor connected to a current path of said transistor, said transistor including a gate insulated from said semiconductor substrate by a gate insulating film formed on said semiconductor substrate and source and drain regions formed in said semiconductor substrate, and said capacitor being formed in a trench in said semiconductor substrate.

Claim 20

A semiconductor memory device according to claim 14, further comprising: an insulating layer formed on said capacitor; a second memory cell pair comprising third and fourth memory cells formed in the spacing between said second one and a third one of said parallel insulative strips; and a word line formed on said insulating layer, said word line electrically connected to said third memory cell.

Claim 21

A semiconductor memory device, comprising: a semiconductor substrate; a plurality of parallel insulative strips formed on a major surface of said semiconductor substrate, said parallel insulative strips extending in a first direction on said major surface and having spacings therebetween; a first memory cell pair comprising first and second memory cells formed in the spacing between first and second ones of said parallel insulative strips, each of said first and second memory cells having a first transistor and a first capacitor connected to a current path of said first transistor, said first transistor including a first gate insulated from said semiconductor substrate by a gate insulating film formed on said semiconductor substrate and source and drain regions formed in said semiconductor substrate, and said first capacitor being formed in a first trench in said semiconductor substrate; a second memory cell pair comprising third and fourth memory cells formed in the spacing between said second one and a third one of said parallel insulative strips, said third and fourth memory cells being shifted in the first direction from said first and second memory cells, each of said third and fourth memory cells having a second transistor including a second gate as a word line and a second capacitor connected to a current path of said second transistor, each of said word lines extending above said first capacitor of one of said first and second memory cells, said second capacitor formed in a second trench in said semiconductor substrate; and first and second insulating films formed on the major surface of said semiconductor substrate, said first insulating film being between said first trenches of said first and second memory cells and said second insulating film being between said second trenches of said third and fourth memory cells, a thickness of said first and second insulating films being less than a thickness of said parallel insulative strips.

Claim 22

A semiconductor memory device, comprising: a semiconductor substrate; a plurality of parallel insulative strips formed on a major surface of said semiconductor substrate, said parallel insulative strips extending in a first direction on said major surface and having spacings therebetween; a first memory cell pair comprising first and second memory cells formed in the spacing between first and second ones of said parallel insulative strips, each of said first and second memory cells having a first transistor and a first capacitor connected to a current path of said first transistor, said first transistor including a first gate insulated from said semiconductor substrate by a gate insulating film formed on said semiconductor substrate and source and drain regions formed in said semiconductor substrate, and said first capacitor being formed in a first trench in said semiconductor substrate; a second memory cell pair comprising third and fourth memory cells formed in the spacing between said second one and a third one of said parallel insulative strips, said third and fourth memory cells being shifted in the first direction from said first and second memory cells, each of said third and fourth memory cells having a second transistor including a second gate as a word line and a second capacitor connected to a current path of said second transistor, each of said word lines extending above said first capacitor of one of said first and second memory cells, said second capacitor formed in a second trench in said semiconductor substrate; and first and second insulating films formed on the major surface of said semiconductor substrate, said first insulating film being between said first trenches of said first and second memory cells and said second insulating film being between said second trenches of said third and fourth memory cells, a thickness of said first and second insulating films being less than a thickness of said parallel insulative strips.