Voltage regulator for programming non-volatile and electrically programmable memory cells

Claim 2

A voltage regulator for programming a plurality of non-volatile memory cells, comprising: a current mirror having an input and an output; a resistive divider having a first input coupled to a first reference voltage, a second input coupled to the output of the current mirror, and an output; an amplifier stage having an input coupled to the output of the resistive divider and an output coupled to the input of the current mirror; a source-follower transistor controlled by said amplifier stage output and coupled to the plurality of non-volatile memory cells through a programming line, the source-follower transistor being further coupled to the input of the current mirror; a first transistor that couples the programming line to a second reference voltage; and a resistive path coupled to the output of the current mirror and the second reference voltage.

Claim 3

The voltage regulator of claim 1, wherein said resistive path comprises a second transistor.

Claim 4

The voltage regulator of claim 2, wherein the second transistor has a drain terminal connected to the output of the current mirror and a source terminal connected to the second reference voltage.

Claim 5

The voltage regulator of claim 1, for programming a plurality of non-volatile memory cells with a pattern of bits to be stored in the plurality of non-volatile memory cells, the voltage regulator further comprising: a network of resistive elements activated according to the pattern of bits, the network of resistive elements being connected between the resistive divider and the second voltage reference; and a resistive path connected in parallel with the network of resistive elements.

Claim 6

The voltage regulator of claim 4, further comprising a decoupling element, connected between a third reference voltage and the programming line, that disconnects the voltage regulator from the programming line when the plurality of non-volatile memory cells are read.

Claim 7

The voltage regulator of claim 1, further comprising a decoupling element, connected between a third reference voltage and the programming line, that disconnects the voltage regulator from the programming line when the plurality of non-volatile memory cells are read.

Claim 8

A voltage regulator for programming a plurality of non-volatile memory cells with a pattern of bits to be stored in the plurality of non-volatile memory cells, the voltage regulator comprising: a current mirror having an input and an output; a resistive divider having a first input coupled to a first reference voltage, a second input coupled to the output of the current mirror, and an output; an amplifier stage having an input coupled to the output of the resistive divider and an output coupled to the input of the current mirror; a source-follower transistor controlled by said amplifier stage output and coupled to the plurality of non-volatile memory cells through a programming line, the source-follower transistor being further coupled to the input of the current mirror; a network of resistive elements activated according the pattern of bits, the network of resistive elements being connected between the resistive divider and a second voltage reference; and a resistive path connected in parallel with the network of resistive elements.

Claim 9

A voltage regulator for programming a plurality of non-volatile memory cells with a pattern of bits to be stored in the plurality of non-volatile memory cells, the voltage regulator comprising: a current mirror having an input and an output; a resistive divider having a first input coupled to a first reference voltage, a second input coupled to the output of the current mirror, and an output; an amplifier stage having an input coupled to the output of the resistive divider and an output coupled to the input of the current mirror; a source-follower transistor controlled by said amplifier stage output and coupled to the plurality of non-volatile memory cells through a programming line, the source-follower transistor being further coupled to the input of the current mirror; a network of resistive elements activated according the pattern of bits, the network of resistive elements being connected between the resistive divider and a second voltage reference; and a resistive path connected in parallel with the network of resistive elements.

Claim 10

The voltage regulator of claim 7, wherein said resistive path includes a MOS transistor with a drain terminal connected to the second input of the resistive divider and a source terminal coupled to the second voltage reference.

Claim 11

The voltage regulator of claim 7, wherein the network of resistive elements comprises a plurality of transistors, and wherein the resistive path comprises a transistor.

Claim 12

The voltage regulator of claim 7, further comprising a decoupling element, connected between a third reference voltage and the programming line, that disconnects the voltage regulator from the programming line when the plurality of non-volatile memory cells are read.

Claim 13

A voltage regulator for programming a plurality of non-volatile memory cells, comprising: a current mirror having an input and an output; a resistive divider having a first input coupled to a first reference voltage, a second input coupled to the output of the current mirror, and an output; an amplifier stage having an input coupled to the output of the resistive divider and an output coupled to the input of the current mirror; a source-follower transistor controlled by said amplifier stage output and coupled to the plurality of non-volatile memory cells through a programming line, the source-follower transistor being further coupled to the input of the current mirror; and a decoupling element, connected between a third reference voltage and the programming line, that disconnects the voltage regulator from the programming line when the plurality of non-volatile memory cells are read.

Claim 14

A voltage regulator for programming a plurality of non-volatile memory cells, comprising: a current mirror having an input and an output; a resistive divider having a first input coupled to a first reference voltage, a second input coupled to the output of the current mirror, and an output; an amplifier stage having an input coupled to the output of the resistive divider and an output coupled to the input of the current mirror; a source-follower transistor controlled by said amplifier stage output and coupled to the plurality of non-volatile memory cells through a programming line, the source-follower transistor being further coupled to the input of the current mirror; and a decoupling element, connected between a third reference voltage and the programming line, that disconnects the voltage regulator from the programming line when the plurality of non-volatile memory cells are read.

Claim 15

The voltage regulator of claim 11, wherein said decoupling element comprises at least two transistors connected serially between the third reference voltage and the programming line.

Claim 16

The voltage regulator of claim 11, wherein each of the at least two transistors of the decoupling element has a body terminal, and wherein the body terminals of the at least two transistors are connected together and to the third reference voltage.

Claim 17

The voltage regulator of claim 11, wherein one of the at least two transistors of the decoupling element is configured as a diode.

Claim 18

The voltage regulator of claim 11, further comprising a disabling transistor, coupled to the output of the amplifier stage and the second reference voltage, that disables the amplifier when the plurality of non-volatile memory cells are read.

Claim 19

A voltage regulator for generating a programming voltage for a plurality of non-volatile memory cells, the voltage regulator comprising: an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor having an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to the plurality of non-volatile memory cells and the second input of the amplifier, the transistor having a bias current; and means for compensating for the bias current so that the programming voltage at the plurality of non-volatile memory cells remains within a predetermined range.

Claim 20

A voltage regulator for generating a programming voltage for a plurality of non-volatile memory cells, the voltage regulator comprising: an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor having an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to the plurality of non-volatile memory cells and the second input of the amplifier, the transistor having a bias current; and means for compensating for the bias current so that the programming voltage at the plurality of non-volatile memory cells remains within a predetermined range.

Claim 21

The voltage regulator of claim 16, wherein the plurality of non-volatile memory cells is to be programmed with patterns of bits to be stored in the plurality of non-volatile memory cells, the plurality of non-volatile memory cells including a group of non-volatile memory cells to be programmed to a high state for each pattern of bits, and wherein the voltage regulator further comprises means for compensating for a number of non-volatile memory cells to be programmed to the high state for each pattern of bits so that the programming voltage at each non-volatile memory cell to be programmed to the high state remains within the predetermined range despite variations in the number of non-volatile memory cells to be programmed to the high state.

Claim 22

The voltage regulator of claim 17, further comprising means for decoupling the output of the transistor from the plurality of non-volatile memory cells when the plurality of non-volatile memory cells are read.

Claim 23

The voltage regulator of claim 16, further comprising means for decoupling the output of the transistor from the plurality of non-volatile memory cells when the plurality of non-volatile memory cells are read.

Claim 24

A voltage regulator for generating a programming voltage for a plurality of non-volatile memory cells to be programmed with patterns of bits to be stored in the plurality of non-volatile memory cells, the plurality of non-volatile memory cells including a group of non-volatile memory cells to be programmed to a high state for each pattern of bits, the voltage regulator comprising: an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor having an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to the plurality of non-volatile memory cells and the second input of the amplifier; and means for compensating for a number of non-volatile memory cells to be programmed to the high state for each pattern of bits so that the programming voltage at each non-volatile memory cell to be programmed to the high state remains within a predetermined range despite variations in the number of non-volatile memory cells to be programmed to the high state.

Claim 25

A voltage regulator for generating a programming voltage for a plurality of non-volatile memory cells to be programmed with patterns of bits to be stored in the plurality of non-volatile memory cells, the plurality of non-volatile memory cells including a group of non-volatile memory cells to be programmed to a high state for each pattern of bits, the voltage regulator comprising: an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor having an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to the plurality of non-volatile memory cells and the second input of the amplifier; and means for compensating for a number of non-volatile memory cells to be programmed to the high state for each pattern of bits so that the programming voltage at each non-volatile memory cell to be programmed to the high state remains within a predetermined range despite variations in the number of non-volatile memory cells to be programmed to the high state.

Claim 26

The voltage regulator of claim 20, further comprising means for decoupling the output of the transistor from the plurality of non-volatile memory cells when the plurality of non-volatile memory cells are read.

Claim 27

A voltage regulator for generating a programming voltage for a plurality of non-volatile memory cells, the voltage regulator comprising: an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor having an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to the plurality of non-volatile memory cells and the second input of the amplifier; and means for decoupling the output of the transistor from the plurality of non-volatile memory cells when the plurality of non-volatile memory cells are read.

Claim 28

A voltage regulator for generating a programming voltage for a plurality of non-volatile memory cells, the voltage regulator comprising: an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor having an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to the plurality of non-volatile memory cells and the second input of the amplifier; and means for decoupling the output of the transistor from the plurality of non-volatile memory cells when the plurality of non-volatile memory cells are read.

Claim 29

The voltage regulator of claim 22, wherein the means for decoupling includes means for causing the programming voltage to be a value equal to a supply voltage minus a threshotd voltage of a decoupling transistor.

Claim 30

The voltage regulator of claim 22, wherein the means for decoupling includes means, coupled between a second voltage reference and the output of the transistor, for connecting the output of the transistor to the second voltage reference.

Claim 31

A voltage regulator for generating a programming voltage for a plurality of non-volatile memory cells, the voltage regulator comprising: an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor having an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to the plurality of non-volatile memory cells and the second input of the amplifier, the transistor having a bias current; and a current mirror having an input coupled to the transistor, and an output coupled to the first input of the amplifier, the current mirror compensating for the bias current of the transistor so that the programming voltage at the plurality of non-volatile memory cells remains within a predetermined range.

Claim 32

A voltage regulator for generating a programming voltage for a plurality of non-volatile memory cells, the voltage regulator comprising: an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor having an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to the plurality of non-volatile memory cells and the second input of the amplifier, the transistor having a bias current; and a current mirror having an input coupled to the transistor, and an output coupled to the first input of the amplifier, the current mirror compensating for the bias current of the transistor so that the programming voltage at the plurality of non-volatile memory cells remains within a predetermined range.

Claim 33

The voltage regulator of claim 25, wherein the plurality of non-volatile memory cells is to be programmed with patterns of bits to be stored in the plurality of non-volatile memory cells, the plurality of non-volatile memory cells including a group of non-volatile memory cells to be programmed to a high state for each pattern of bits, the voltage regulator further comprising a resistive path, coupled between the second input of the amplifier and a second reference voltage, that compensates for a number of non-volatile memory cells to be programmed to the high state for each pattern of bits so that the programming voltage at each non-volatile memory cell to be programmed to the high state remains within the predetermined range despite variations in the number of non-volatile memory cells to be programmed to the high state.

Claim 34

The voltage regulator of claim 25, further comprising at least one transistor, coupled between the output of the transistor and a third reference voltage, that decouples the output of the transistor from the non-volatile memory cells when the plurality of non-volatile memory cells are read.

Claim 35

The voltage regulator of claim 25, further comprising at least one transistor, coupled between the output of the transistor and a second reference voltage, that decouples the output of the transistor from the non-volatile memory cells when the plurality of non-volatile memory cells are read.

Claim 36

A voltage regulator for generating a programming voltage for a plurality of non-volatile memory cells to be programmed with patterns of bits to be stored in the plurality of non-volatile memory cells, the plurality of non-volatile memory cells including a group of non-volatile memory cells to be programmed to a high state for each pattern of bits, the voltage regulator comprising: an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor having an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to the plurality of non-volatile memory cells and the second input of the amplifier; and a compensation resistive element, coupled between the first input of the amplifier and a second reference voltage, that compensates for a number of non-volatile memory cells to be programmed to the high state for each pattern of bits so that the programming voltage at each non-volatile memory cell to be programmed to the high state remains within a predetermined range despite variations in the number of non-volatile memory cells to be programmed to the high state.

Claim 37

A voltage regulator for generating a programming voltage for a plurality of non-volatile memory cells to be programmed with patterns of bits to be stored in the plurality of non-volatile memory cells, the plurality of non-volatile memory cells including a group of non-volatile memory cells to be programmed to a high state for each pattern of bits, the voltage regulator comprising: an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor having an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to the plurality of non-volatile memory cells and the second input of the amplifier; and a compensation resistive element, coupled between the first input of the amplifier and a second reference voltage, that compensates for a number of non-volatile memory cells to be programmed to the high state for each pattern of bits so that the programming voltage at each non-volatile memory cell to be programmed to the high state remains within a predetermined range despite variations in the number of non-volatile memory cells to be programmed to the high state.

Claim 38

The voltage regulator of claim 29, further comprising at least one transistor, coupled between the output of the transistor and a third reference voltage, that decouples the output of the transistor from the non-volatile memory cells when the plurality of non-volatile memory cells are read.

Claim 39

A voltage regulator for generating a programming voltage for a plurality of non-volatile memory cells, the voltage regulator comprising: an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor having an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to the plurality of non-volatile memory cells and the second input of the amplifier; and a decoupling element, coupled between the output of the transistor and a second reference voltage, that decouples the output of the transistor from the non-volatile memory cells when the plurality of non-volatile memory cells are read.

Claim 40

A voltage regulator for generating a programming voltage for a plurality of non-volatile memory cells, the voltage regulator comprising: an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor having an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to the plurality of non-volatile memory cells and the second input of the amplifier; and a decoupling element, coupled between the output of the transistor and a second reference voltage, that decouples the output of the transistor from the non-volatile memory cells when the plurality of non-volatile memory cells are read.

Claim 41

The voltage regulator of claim 31, wherein the decoupling element includes at least one decoupling transistor coupled between the output of the transistor and the second reference voltage.

Claim 42

The voltage regulator of claim 31, wherein the decoupling element includes: a first decoupling transistor having a first terminal coupled to the second reference voltage, a second terminal, and a gate terminal coupled to the second reference voltage; and a second decoupling transistor, having a first terminal coupled to the second terminal of the first decoupling transistor, and a second terminal coupled to the output of the transistor.

Claim 43

A memory device, comprising: a plurality of memory cells; and a voltage regulator, coupled to the plurality of memory cells, that provides a programming voltage for the plurality of memory cells, the voltage regulator including; an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor having an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to the plurality of memory cells and the second input of the amplifier, the transistor having a bias current; and a current mirror having an input coupled to the transistor, and an output coupled to the second input of the amplifier, the current mirror compensating for the bias current of the transistor so that the programming voltage at the plurality of memory cells remains within a predetermined range.

Claim 44

A memory device, comprising: a plurality of memory cells; and a voltage regulator, coupled to the plurality of memory cells, that provides a programming voltage for the plurality of memory cells, the voltage regulator including; an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor having an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to the plurality of memory cells and the second input of the amplifier, the transistor having a bias current; and a current mirror having an input coupled to the transistor, and an output coupled to the second input of the amplifier, the current mirror compensating for the bias current of the transistor so that the programming voltage at the plurality of memory cells remains within a predetermined range.

Claim 45

The memory device of claim 30, wherein the plurality of memory cells is to be programmed with patterns of bits to be stored in the plurality of memory cells, the plurality of memory cells including a group of memory cells to be programmed to a high state for each pattern of bits, the voltage regulator further comprising a resistive path, coupled between the second input of the amplifier and a second reference voltage, that compensates for a number of memory cells to be programmed to the high state for each pattern of bits so that the programming voltage at each memory cell to be programmed to the high state remains within the predetermined range despite variations in the number of memory cells to be programmed to the high state.

Claim 46

The memory device of claim 35, wherein the voltage regulator further includes at least one transistor, coupled between the output of the transistor and a third reference voltage, that decouples the output of the transistor from the plurality of memory cells when the plurality of memory cells are read.

Claim 47

The memory device of claim 34, wherein the voltage regulator further includes at least one transistor, coupled between the output of the transistor and a third reference voltage, that decouples the output of the transistor from the plurality of memory cells when the plurality of memory cells are read.

Claim 48

A memory device, comprising: a plurality of memory cells; and a voltage regulator, coupled to the plurality of memory cells, that provides a programming voltage for the plurality of memory cells, the plurality of memory cells to be programmed with patterns of bits to be stored in the plurality of memory cells, the plurality of memory cells including a group of memory cells to be programmed to a high state for each pattern of bits, and wherein the voltage regulator includes; an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor, with an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to plurality of memory cells and the second input of the amplifier; and a compensation element, coupled between the first input of the amplifier and a second reference voltage, that compensates for a number of memory cells to be programmed to the high state for each pattern of bits so that the programming voltage at each memory cell to be programmed to the high state remains within a predetermined range despite variations in the number of memory cells to be programmed to the high state.

Claim 49

A memory device, comprising: a plurality of memory cells; and a voltage regulator, coupled to the plurality of memory cells, that provides a programming voltage for the plurality of memory cells, the plurality of memory cells to be programmed with patterns of bits to be stored in the plurality of memory cells, the plurality of memory cells including a group of memory cells to be programmed to a high state for each pattern of bits, and wherein the voltage regulator includes; an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor, with an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to plurality of memory cells and the second input of the amplifier; and a compensation element, coupled between the first input of the amplifier and a second reference voltage, that compensates for a number of memory cells to be programmed to the high state for each pattern of bits so that the programming voltage at each memory cell to be programmed to the high state remains within a predetermined range despite variations in the number of memory cells to be programmed to the high state.

Claim 50

The memory device of claim 38, wherein the voltage regulator further includes at least one transistor, coupled between the output of the transistor and a third reference voltage, that decouples the output of the transistor from the plurality of memory cells when the plurality of memory cells are read.

Claim 51

A memory device, comprising: a plurality of memory cells; and a voltage regulator, coupled to the plurality of memory cells, that provides a programming voltage for the plurality of memory cells, the voltage regulator including; an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor having an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to the plurality of memory cells and the second input of the amplifier; and a decoupling element, coupled between the output of the transistor and a second reference voltage, that decouples the output of the transistor from the plurality of memory cells when the plurality of memory cells are read.

Claim 52

A memory device, comprising: a plurality of memory cells; and a voltage regulator, coupled to the plurality of memory cells, that provides a programming voltage for the plurality of memory cells, the voltage regulator including; an amplifier having a first input coupled to a reference voltage, a second input, and an output; a transistor having an input coupled to the output of the amplifier, and an output that generates the programming voltage, the output of the transistor being coupled to the plurality of memory cells and the second input of the amplifier; and a decoupling element, coupled between the output of the transistor and a second reference voltage, that decouples the output of the transistor from the plurality of memory cells when the plurality of memory cells are read.

Claim 53

The memory device of claim 40, wherein the decoupling element includes at least one decoupling transistor coupled between the output of the transistor and the second reference voltage.

Claim 54

The memory device of claim 40, wherein the decoupling element includes: a first decoupling transistor having a first terminal coupled to the second reference voltage, a second terminal and a gate terminal coupled to the second reference voltage; and a second decoupling transistor, having a first terminal coupled to the second terminal of the first decoupling transistor, and a second terminal coupled to the output of the transistor.