US4804865A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fast voltage reference stabilization circuit
Assignee: Intersil Corp
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Filing: 1987-03-19
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Granted: 1989-02-14
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Expires: 2007-03-19
Abstract
Abstract A circuit for providing a fast stabilization of the reference voltage level produced by a reference generation circuit includes a clamping circuit which clamps the refernece node at a voltage approximately equal to the voltage produced by the reference generation circuit when the reference voltage level is disabled. When the reference generation circuit is enabled, the reference node has to be pulled only slightly to reach the proper reference voltage, thereby increasing the speed of the device and the clamping circuit is turned off.
Inventors
- 👤 II Jack E. Clark
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 05:44
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G11; G11C; G11C7/00; G11C7/06; Y; Y10; Y10S; Y10S136/00; Y10S136/291; Y10S136/293
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
76 words
A voltage reference stabilization circuit, comprising: reference voltage generation means for supplying a reference voltage at a reference node; enable means connected to said reference voltage generation means for enabling and disabling said reference voltage generation means; and clamping means connected to said reference node and said enable means for clamping said reference node at a clamp voltage approximately equal to said reference voltage when said reference voltage generation means is disabled by said enable means.
Claim 2
Dependent Claim
76 words
A voltage reference stabilization circuit, comprising: reference voltage generation means for supplying a reference voltage at a reference node; enable means connected to said reference voltage generation means for enabling and disabling said reference voltage generation means; and clamping means connected to said reference node and said enable means for clamping said reference node at a clamp voltage approximately equal to said reference voltage when said reference voltage generation means is disabled by said enable means.
Claim 3
Dependent Claim
26 words
The circuit of claim 1, wherein said enable means enables and disables said clamping means when said reference voltage generation means is disabled and enabled respectively.
Claim 4
Dependent Claim
35 words
The circuit of claim 2, wherein said clamping means has at least one switch means connected between a voltage source and said reference node for connecting and disconnecting said voltage source and said reference node.
Claim 5
Dependent Claim
19 words
The circuit of claim 3, wherein said switch means is a transistor that is actuated by said enable means.
Claim 6
Dependent Claim
43 words
The circuit of claim 1, wherein said enable means includes enable signal generator means for generating enable and disable reference signals, and at least two switch means for disabling and tri-stating said reference voltage generation means in response to said disable reference signal.
Claim 7
Dependent Claim
12 words
The circuit of claim 5, wherein said tri-state switch means are transistors.
Claim 8
Dependent Claim
40 words
The circuit of claim 6, wherein a first said transistor is connected between a first voltage level and said reference voltage generation means, and a second transistor is connected between the reference voltage generation means and a second voltage level.
Claim 9
Dependent Claim
32 words
The circuit of claim 7, wherein the first transistor is turned on and off and the clamping means is turned off and on respectively in response to the same enable reference signal.
Claim 10
Dependent Claim
31 words
The circuit of claim 1, wherein the clamping means includes a plurality of transistors connected to series for providing a predetermined voltage drop between the supply voltage and said reference node.
Claim 11
Dependent Claim
83 words
A voltage reference stabilization circuit, comprising: reference voltage generator means having an output reference node for generating a reference voltage, and stabilizing means connected to said reference voltage generator means, ground and a voltage source for eliminating a current path to ground through said reference voltage generator means and providing a voltage at said reference node approximately equal to said reference voltage when said reference voltage generator means is turned off by eliminating a current path to ground through said reference voltage generator.
Claim 12
Dependent Claim
83 words
A voltage reference stabilization circuit, comprising: reference voltage generator means having an output reference node for generating a reference voltage, and stabilizing means connected to said reference voltage generator means, ground and a voltage source for eliminating a current path to ground through said reference voltage generator means and providing a voltage at said reference node approximately equal to said reference voltage when said reference voltage generator means is turned off by eliminating a current path to ground through said reference voltage generator.
Claim 13
Dependent Claim
35 words
The circuit of claim 10, wherein said stabilizing means includes tri-stating means for tri-stating said reference voltage generator means such that no current path to ground exists when said reference voltage generator means is tri-stated.
Claim 14
Dependent Claim
32 words
The circuit of claim of 11, wherein said stabilizing means includes clamping means for providing a clamped voltage approximately equal to said reference voltage when said reference voltage generator means is tri-stated.
Claim 15
Dependent Claim
48 words
The circuit of claim 1, wherein said enable means includes two switch means connected between said reference voltage generation means and first and second voltage levels respectively, and enable signal generation means for generating enable and disable reference signals to activate and deactivate each of said switch means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-14 | 1992-08-15 | 1993-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-14 | 1996-08-15 | 1997-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-14 | 2000-08-15 | 2001-02-14 | $7700.00 | Window Closed / Lapsed |