EP0525679A2
Expired / Lapsed
EP
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Writing control circuit employed in non-volatile semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1992-07-24
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Granted: —
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Expires: 2012-07-24
Abstract
Abstract 5 n7 A write control circuit (20) is provided for supplying a gate of an n-channel enhancement-type writing transistor (15) with a voltage corresponding to data when the data is written. The circuit (20) comprises a reference potential-generation circuit (21), a a differential amplifier (22), and a feedback circuit (23). The reference potential-generation circuit (21) generates a reference potential (VR) substantially equal to the upper limit of that high level of each of the bit lines (13) which is assumed at the time of writing. The differential amplifier (22) has an input terminal to be supplied with the reference potential (VR). A write voltage (SW or Vpp) serving as an operation voltage is applied to the amplifier (22). The feedback circuit (23) is connected between the other input terminal and output terminal of the differential amplifier (22). The feedback circuit (23) generates, under the control of the differential amplifier (22), a write control voltage (VA) higher than the reference potential (VR) by the threshold voltage of the writing transistor (15), and applies the write control voltage (VA) to the gate of the writing transistor (15). Also, the feedback circuit (23) feeds a voltage (VB) obtained by reducing the write control voltage (VA), back to the other input terminal of the differential amplifier (22).
Inventors
- 👤 Shigeru C/O Intellectual Property Div. Atsumi
- 👤 Hironori C/O Intellectual Property Div. Banba
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 16:14
CPC Classifications
G; G11; G11C; G11C16/00; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F3/242; G05F3/26; G05F3/262; G11C16/02; G11C16/06; G11C16/10; G11C16/30; G11C5/00; G11C5/14; G11C5/147
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
342 words
A non-volatile semiconductor memory device comprising a memory cell array having non-volatile memory cells arranged in rows and columns, each memory cell having a control gate, a floating gate, a source, and a drain; word lines each connected to the control gates of those memory cells of the memory cell array which are arranged in the same row; bit lines being perpendicular to the word lines, and each connected to the drains of those memory cells of the memory cell array which are arranged in the same column; column-selecting transistors each having a current path, which has one end thereof connected to a corresponding one of the bit lines and the other end thereof connected in common to one another; an n-channel enhancement-type writing transistor having a current path, which has an end thereof connected to the other end of each of the column-selecting transistors, and the other end thereof connected to a writing voltage source; and a write control circuit for supplying the gate of the writing transistor with a voltage corresponding to data when the data is written, characterized in that the write control circuit (20) has reference potential-generation means (21) for generating a reference potential (VR), differential amplifier means (22) to be supplied with a write voltage serving as an operation voltage, from the writing voltage source (SW or Vpp), the differential amplifier means (22) having an input terminal to be supplied with the reference potential (VR) from the reference potential-generation means (21), and feedback means (23) connected between the other input terminal and output terminal of the differential amplifier means (22), the feedback means generating, under the control of the differential amplifier means (22), a write control voltage (VA) higher than the reference potential (VA) by the threshold voltage of the n-channel enhancement-type writing transistor (15), and applying the write control voltage (VA) to the gate of the writing transistor (15), the feedback means feeding a voltage (VB) obtained by reducing the write control voltage (VA), back to the other input terminal of the differential amplifier means (22).
Claim 2
Dependent Claim
342 words
A non-volatile semiconductor memory device comprising a memory cell array having non-volatile memory cells arranged in rows and columns, each memory cell having a control gate, a floating gate, a source, and a drain; word lines each connected to the control gates of those memory cells of the memory cell array which are arranged in the same row; bit lines being perpendicular to the word lines, and each connected to the drains of those memory cells of the memory cell array which are arranged in the same column; column-selecting transistors each having a current path, which has one end thereof connected to a corresponding one of the bit lines and the other end thereof connected in common to one another; an n-channel enhancement-type writing transistor having a current path, which has an end thereof connected to the other end of each of the column-selecting transistors, and the other end thereof connected to a writing voltage source; and a write control circuit for supplying the gate of the writing transistor with a voltage corresponding to data when the data is written, characterized in that the write control circuit (20) has reference potential-generation means (21) for generating a reference potential (VR), differential amplifier means (22) to be supplied with a write voltage serving as an operation voltage, from the writing voltage source (SW or Vpp), the differential amplifier means (22) having an input terminal to be supplied with the reference potential (VR) from the reference potential-generation means (21), and feedback means (23) connected between the other input terminal and output terminal of the differential amplifier means (22), the feedback means generating, under the control of the differential amplifier means (22), a write control voltage (VA) higher than the reference potential (VA) by the threshold voltage of the n-channel enhancement-type writing transistor (15), and applying the write control voltage (VA) to the gate of the writing transistor (15), the feedback means feeding a voltage (VB) obtained by reducing the write control voltage (VA), back to the other input terminal of the differential amplifier means (22).
Claim 3
Dependent Claim
67 words
The non-volatile semiconductor memory device according to claim 1, characterized in that the reference potential-generation means (21) has a plurality of load elements (R1, R2, 51-1, 51-2, ... 51-n, 61, 62-1, 62-2, ..., 62-n) connected in series between the writing voltage source (SW or Vpp) and a ground terminal (Vss), the reference potential-generation means out-putting the reference potential (VR) from a connection node between the load elements.
Claim 4
Dependent Claim
22 words
The non-volatile semiconductor memory device according to claim 2, characterized in that each of the load elements includes a resistor (R1, R2).
Claim 5
Dependent Claim
29 words
The non-volatile semiconductor memory device according to claim 2, characterized in that each of the load elements includes a transistor (51-1, 51-2, ..., 51-n) having a diode connection structure.
Claim 6
Dependent Claim
43 words
The non-volatile semiconductor memory device according to claim 4, characterized in that the transistor (51-1, 51-2, ..., 51-n) is of an enhancement type, and has a source thereof connected to a back gate thereof, and a gate thereof connected to a drain thereof.
Claim 7
Dependent Claim
30 words
The non-volatile semiconductor memory device according to claim 2, characterized in that the load elements include a resistor (61) and a transistor (62-1, ..., 62-n) having a diode connection structure.
Claim 8
Dependent Claim
42 words
The non-volatile semiconductor memory device according to claim 6, characterized in that the transistor (61-1, ..., 61-n) is of an enhancement type, and has a source thereof connected to a back gate thereof, and a gate thereof connected to a drain thereof.
Claim 9
Dependent Claim
87 words
The non-volatile semiconductor memory device according to claim 1, characterized in that the reference potential generation-means (21) has a constant-current source (65) having an end connected to the writing voltage source (SW or Vpp), and a first diode (64) having a cathode connected to the other end of the constant-current source (65), and an anode connected to a ground terminal (Vss), the reference potential (VR) being output from a connection node between the other end of the constant-current source and the cathode of the first diode (64).
Claim 10
Dependent Claim
47 words
The non-volatile semiconductor memory device according to claim 8, characterized in that the constant-current source (65) includes a depletion-type transistor (63) having a drain connected to the writing voltage source (SW or Vpp), a gate and a source connected to the cathode of the first diode (64).
Claim 11
Dependent Claim
42 words
The non-volatile semiconductor memory device according to claim 8, characterized by further comprising a second diode (66) having an anode connected to the other end of the constant-current source (65), and a cathode connected to the cathode of the first diode (64).
Claim 12
Dependent Claim
25 words
The non-volatile semiconductor memory device according to claim 1, characterized in that the differential amplifier means includes a current-mirror-load type CMOS differential amplifier circuit (22).
Claim 13
Dependent Claim
150 words
The non-volatile semiconductor memory device according to claim 1, characterized in that the feedback means (23) is provided with a p-channel enhancement-type transistor (29) having a source connected to the writing voltage source (SW or Vpp), and a gate to be supplied with an output potential from the differential amplifier means; an n-channel enhancement-type transistor (30) having a gate and a drain connected to the drain of the p-channel enhancement-type transistor (29); and a first resistor (31) connected between the source of the n-channel enhancement-type transistor (30) and a ground terminal, a junction between the drain of the p-channel enhancement-type transistor (29) and the drain of the n-channel enhancement-type transistor (30) being connected to the gate of the writing transistor (15), and a junction between the source of the n-channel enhancement-type transistor (30) and the first resistor being connected to the other input terminal of the differential amplifier means (22).
Claim 14
Dependent Claim
56 words
The non-volatile semiconductor memory device according to claim 12, characterized by further comprising a second resistor (34) connected between the source of the n-channel enhancement-type transistor (30) and the first resistor (31), and characterized in that a junction between the resistors (31, 34) is connected to the other input terminal of the differential amplifier means (22).
Claim 15
Dependent Claim
114 words
The non-volatile semiconductor memory device according to claim 12, characterized by further comprising a first n-channel intrinsic-type transistor (32) having a drain and a gate connected to the drain of the p-channel enhancement-type transistor (29), and a source connected to the drain and gate of the n-channel enhancement-type transistor (30); and a second n-channel intrinsic-type transistor (32) having a drain connected to the writing voltage source (SW or Vpp), and a gate connected to a junction between the drain of the p-channel enhancement-type transistor (29) and the drain of the first n-channel intrinsic-type transistor (32), the source of the second n-channel intrinsic-type transistor (33) being connected to the gate of the writing transistor (15).
References Cited (Backward Citations)
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