US5519355A — High speed boundary scan multiplexer

Claim 1

Independent Claim 135 words

A semiconductor chip comprising: an I/O region proximate an edge of the chip; a core region located inside said I/O region; and an input cell located in said I/O region, comprising an input pad for receiving an input signal; a first conductive line coupling said input cell to a first portion of said core region; a second conductive line coupling said input cell to a second portion of said core region; a high-speed path connecting said input pad to said first line for passing said input signal to said first line; a low-speed path connecting said second line to said first line for passing a data signal from said core region to said first line; and means connected to each of said paths for selectively connecting said first or second path to said first line.

Claim 2

Dependent Claim 135 words

A semiconductor chip comprising: an I/O region proximate an edge of the chip; a core region located inside said I/O region; and an input cell located in said I/O region, comprising an input pad for receiving an input signal; a first conductive line coupling said input cell to a first portion of said core region; a second conductive line coupling said input cell to a second portion of said core region; a high-speed path connecting said input pad to said first line for passing said input signal to said first line; a low-speed path connecting said second line to said first line for passing a data signal from said core region to said first line; and means connected to each of said paths for selectively connecting said first or second path to said first line.

Claim 3

Dependent Claim 23 words

The input cell of claim 1 wherein said first and second paths each includes a transfer gate switchable between conductive and non-conductive states.

Claim 4

Dependent Claim 27 words

The input cell of claim 2 wherein each of said gates includes at least one field effect transistor (FET) having a control electrode connected to said means.

Claim 5

Dependent Claim 29 words

The input cell of claim 3 wherein the FET in said first path has a conduction area greater than the conduction area of the FET in said second path.

Claim 6

Dependent Claim 34 words

The input cell of claim 4 further comprising: a third conductive line connecting said input cell to said core region; wherein said means connects said third line to the control electrode of said FETs.

Claim 7

Dependent Claim 58 words

The input cell of claim 5 wherein said first path includes first and second FETs, the first FET being responsive to a signal of a first polarity for conducting current between its source and drain terminals and the second FET being responsive to a signal of a second polarity for conducting current between its source and drain terminals.

Claim 8

Dependent Claim 58 words

The input cell of claim 6 wherein said second path includes third and fourth FETs, the third FET being responsive to a signal of a first polarity for conducting current between its source and drain terminals and the fourth FET being responsive to a signal of a second polarity for conducting current between its source and drain terminals.

Claim 9

Dependent Claim 42 words

The input cell of claim 7 wherein the control electrode of the first FET is connected to the control electrode of the third FET and the control electrode of the second FET is connected to the control electrode of the fourth FET.

Claim 10

Dependent Claim 44 words

The input cell of claim 8, wherein said means includes: an inverter connected between the third line and the control electrodes of the first and third FETs; wherein said third line is connected directly to the control electrodes of the second and fourth FETs.

Claim 11

Dependent Claim 95 words

A semiconductor chip comprising: an I/O region proximate an edge of the chip; a core region located inside said I/O region; and an input cell located in said I/O region including: an input pad for receiving an input signal; a first conductive line coupling said input cell to a first portion of said core region; a second conductive line coupling said input cell to a second portion of said core region; and a multiplexer having inputs connected to said input pad and second conductive line and having an output connected to said first conductive line.

Claim 12

Dependent Claim 95 words

A semiconductor chip comprising: an I/O region proximate an edge of the chip; a core region located inside said I/O region; and an input cell located in said I/O region including: an input pad for receiving an input signal; a first conductive line coupling said input cell to a first portion of said core region; a second conductive line coupling said input cell to a second portion of said core region; and a multiplexer having inputs connected to said input pad and second conductive line and having an output connected to said first conductive line.

Claim 13

Dependent Claim 78 words

In a semiconductor chip with an I/O region and a core region, an input cell within said I/O region, comprising: an input pad; a first conductive line coupling said input cell to a first portion of said core region; a second conductive line coupling said input cell to a second portion of said core region; and a multiplexer having inputs connected to said input pad and to said first line and an output connected to said second line.

Claim 14

Dependent Claim 78 words

In a semiconductor chip with an I/O region and a core region, an input cell within said I/O region, comprising: an input pad; a first conductive line coupling said input cell to a first portion of said core region; a second conductive line coupling said input cell to a second portion of said core region; and a multiplexer having inputs connected to said input pad and to said first line and an output connected to said second line.

Claim 15

Dependent Claim 14 words

The input cell of claim 11 further comprising: ESD transistors connected to said pad.

Claim 16

Dependent Claim 112 words

In a semiconductor chip with an I/O region and a core region, an input cell within said I/O region, said cell having a generally rectangular layout and comprising: an input pad; ESD transistors connected to said input pad; first and second conductive lines connected to said core region; a multiplexer having inputs connected to said input pad and to said first line and an output connected to said second line, wherein: said multiplexer includes a first transistor connected between said pad and said second line and a second transistor connected between said first line and said second line; and said first and second transistors are positioned between two of said ESD transistors.

Claim 17

Dependent Claim 112 words

In a semiconductor chip with an I/O region and a core region, an input cell within said I/O region, said cell having a generally rectangular layout and comprising: an input pad; ESD transistors connected to said input pad; first and second conductive lines connected to said core region; a multiplexer having inputs connected to said input pad and to said first line and an output connected to said second line, wherein: said multiplexer includes a first transistor connected between said pad and said second line and a second transistor connected between said first line and said second line; and said first and second transistors are positioned between two of said ESD transistors.

Claim 18

Dependent Claim 23 words

The input cell of claim 13, wherein said first transistor has a conduction area greater than the conduction area of said second transistor.

Claim 19

Dependent Claim 19 words

The input cell of claim 14 wherein said input pad is positioned in the center of said rectangular layout.

Claim 20

Dependent Claim 18 words

The input cell of claim 15 wherein said ESD transistors are positioned on opposite sides of said pad.

Claim 21

Dependent Claim 69 words

In a semiconductor chip including logic elements in a core region and an input cell in an I/O region, comprising: an input pad; a first conductive line coupling said input cell to a first portion of said core region; a second conductive line coupling said input cell to a second portion of said core region; and a circuit connected to said input pad and first and second conductive lines.

Claim 22

Dependent Claim 69 words

In a semiconductor chip including logic elements in a core region and an input cell in an I/O region, comprising: an input pad; a first conductive line coupling said input cell to a first portion of said core region; a second conductive line coupling said input cell to a second portion of said core region; and a circuit connected to said input pad and first and second conductive lines.

Claim 23

Dependent Claim 35 words

The input cell of claim 17 wherein said circuit is a multiplexer having first and second inputs connected to said input pad and first line, respectively, and having an output connected to said second line.

Claim 24

Dependent Claim 57 words

The input cell of claim 18 further comprising: a third conductive line connecting said circuit to selected ones of said logic elements; wherein said multiplexer has a third input for controlling whether said input pad or said first line is connected to said second line; and wherein said third input is connected to said third conductive line.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1999-05-21	1999-11-20	2000-05-21	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2003-05-21	2003-11-20	2004-05-21	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2007-05-21	2007-11-20	2008-05-21	$7700.00	Window Closed / Lapsed

High speed boundary scan multiplexer

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