Read and write data aligner and method

Claim 1

An apparatus for writing segments of data from a host bus to a buffer, the host bus coupled to a first data path having N+1 segment lanes D1(n), for n=0 through N, each segment lane D1(n) for transferring a segment of data, and the buffer coupled to a second data path having N+1 segment lanes D2(n), for n=0 through N, each segment lane D2(n) for transferring a segment of data, comprising: a control resource having a control output for generating a first control signal and a second control signal which map segments of data from the first data path to the second data path without redundant accesses of segments of data to be transferred, the second data path having a fixed number of the segments of data to be transferred, and the first data path having a selected number and a selected alignment of the segments of data to be transferred; a first stage including, a plurality of first stage inputs, coupled to the control resource and the segment lanes D1(n), for n=0 through N, associated with the first data path, for receiving at least a segment of data at a selected first stage input among the plurality of first stage inputs, and a plurality of first stage outputs for supplying the segment of data at a selected first stage output among the plurality of first stage outputs in response to the first control signal; and a second stage including, a plurality of second stage inputs coupled to the control resource and a subset of the plurality of first stage outputs, for receiving the segment of data at a selected second stage input among the plurality of second stage inputs, and a plurality of second stage outputs for supplying the segment of data at a selected second stage output among the plurality of second stage outputs in response to the second control signal and coupling the segment of data to the segment lanes associated with the second data path, the second stage capable of queuing and storing segments of data for selectively aligning the segments of data on selected segment lanes of the second data path.

Claim 2

An apparatus for writing segments of data from a host bus to a buffer, the host bus coupled to a first data path having N+1 segment lanes D1(n), for n=0 through N, each segment lane D1(n) for transferring a segment of data, and the buffer coupled to a second data path having N+1 segment lanes D2(n), for n=0 through N, each segment lane D2(n) for transferring a segment of data, comprising: a control resource having a control output for generating a first control signal and a second control signal which map segments of data from the first data path to the second data path without redundant accesses of segments of data to be transferred, the second data path having a fixed number of the segments of data to be transferred, and the first data path having a selected number and a selected alignment of the segments of data to be transferred; a first stage including, a plurality of first stage inputs, coupled to the control resource and the segment lanes D1(n), for n=0 through N, associated with the first data path, for receiving at least a segment of data at a selected first stage input among the plurality of first stage inputs, and a plurality of first stage outputs for supplying the segment of data at a selected first stage output among the plurality of first stage outputs in response to the first control signal; and a second stage including, a plurality of second stage inputs coupled to the control resource and a subset of the plurality of first stage outputs, for receiving the segment of data at a selected second stage input among the plurality of second stage inputs, and a plurality of second stage outputs for supplying the segment of data at a selected second stage output among the plurality of second stage outputs in response to the second control signal and coupling the segment of data to the segment lanes associated with the second data path, the second stage capable of queuing and storing segments of data for selectively aligning the segments of data on selected segment lanes of the second data path.

Claim 14

An apparatus for reading segments of data from a buffer to a host bus, the host bus coupled to a first data path having N+1 segment lanes D1(n), for n=0 through N, each segment lane D1(n) for transferring a segment of data, and the buffer coupled to a second data path having N+1 segment lanes D2(n), for n=0 through N, each segment lane D2(n) for transferring a segment of data, comprising: a control resource having a control output for generating a first control signal and a second control signal which map segments of data from the second data path to the first data path without redundant accesses of segments of data to be transferred, the first data path having a selected number and a selected alignment of the segments of data to be transferred, and the second data path having a fixed number of the segments of data to be transferred; a first stage including a plurality of first stage inputs, coupled to the control resource and a subset of the segment lanes D2(n), for n=1 through N, associated with the second data path, for receiving at least a segment of data at a selected first stage input among the plurality of first stage inputs, and a plurality of first stage outputs for supplying the segment of data at a selected first stage output among the plurality of first stage outputs in response to the first control signal; and a second stage including, a plurality of second stage inputs coupled to the control resource and at least a subset of the plurality of first stage outputs and the segment lanes coupled to the plurality of first stage inputs, for receiving the segment of data at a selected second stage input among the plurality of second stage inputs, and a plurality of second stage outputs for supplying the segment of data at a selected second stage output among the plurality of second stage outputs in response to the second control signal and coupling the segment of data to the segment lanes associated with the first data path where the first stage is capable of queuing and storing segments of data for selectively aligning the segments of data on selected segment lanes of the first data path.

Claim 15

An apparatus for reading segments of data from a buffer to a host bus, the host bus coupled to a first data path having N+1 segment lanes D1(n), for n=0 through N, each segment lane D1(n) for transferring a segment of data, and the buffer coupled to a second data path having N+1 segment lanes D2(n), for n=0 through N, each segment lane D2(n) for transferring a segment of data, comprising: a control resource having a control output for generating a first control signal and a second control signal which map segments of data from the second data path to the first data path without redundant accesses of segments of data to be transferred, the first data path having a selected number and a selected alignment of the segments of data to be transferred, and the second data path having a fixed number of the segments of data to be transferred; a first stage including a plurality of first stage inputs, coupled to the control resource and a subset of the segment lanes D2(n), for n=1 through N, associated with the second data path, for receiving at least a segment of data at a selected first stage input among the plurality of first stage inputs, and a plurality of first stage outputs for supplying the segment of data at a selected first stage output among the plurality of first stage outputs in response to the first control signal; and a second stage including, a plurality of second stage inputs coupled to the control resource and at least a subset of the plurality of first stage outputs and the segment lanes coupled to the plurality of first stage inputs, for receiving the segment of data at a selected second stage input among the plurality of second stage inputs, and a plurality of second stage outputs for supplying the segment of data at a selected second stage output among the plurality of second stage outputs in response to the second control signal and coupling the segment of data to the segment lanes associated with the first data path where the first stage is capable of queuing and storing segments of data for selectively aligning the segments of data on selected segment lanes of the first data path.

Claim 33

A device for transferring data units from a host system, having a host bus having a plurality of segment data lanes, to a network, comprising: a bus interface, coupled to the host bus, for transferring a data unit on each segment data lane in a subset of the plurality of segment data lanes during a bus write cycle; means for receiving a valid data unit signal from the host system; a buffer, having a plurality of memory locations, for storing each data unit; a data path between the bus interface and the buffer; a network controller, coupled to the buffer and the network, for transferring a data unit between the buffer and the network; and a data aligner, in the data path, for controlling alignment of each data unit in the data path in response to the valid data unit signal so that the data units having a selected width and selected alignment are transferred on the subset and sequentially stored in the plurality of buffer memory locations having a fixed width and fixed alignment without requiring redundant writes of any transferred data unit in the subset.

Claim 34

A device for transferring data units from a host system, having a host bus having a plurality of segment data lanes, to a network, comprising: a bus interface, coupled to the host bus, for transferring a data unit on each segment data lane in a subset of the plurality of segment data lanes during a bus write cycle; means for receiving a valid data unit signal from the host system; a buffer, having a plurality of memory locations, for storing each data unit; a data path between the bus interface and the buffer; a network controller, coupled to the buffer and the network, for transferring a data unit between the buffer and the network; and a data aligner, in the data path, for controlling alignment of each data unit in the data path in response to the valid data unit signal so that the data units having a selected width and selected alignment are transferred on the subset and sequentially stored in the plurality of buffer memory locations having a fixed width and fixed alignment without requiring redundant writes of any transferred data unit in the subset.

Claim 35

A device for transferring data units from a network to a host system having a host bus having a plurality of segment data lanes, comprising: a bus interface, coupled to the host bus, for transferring a data unit on each segment data lane during a bus read cycle; means for receiving a valid data unit signal from the host system; a buffer, having a plurality of memory locations, for storing each data unit; a data path between the bus interface and the buffer; a network controller, coupled to the buffer and the network, for transferring data units between the network and the buffer; and a data aligner, in the data path, for controlling alignment of each data unit in the data path in response to the valid data unit signal so that the data units having a fixed width are transferred on a subset of the plurality of segment data lanes to form data units of a selected width and a selected alignment, each segment lane in the subset transferring a data unit, without requiring redundant reads of any transferred data unit in the subset.

Claim 36

A device for transferring data units from a network to a host system having a host bus having a plurality of segment data lanes, comprising: a bus interface, coupled to the host bus, for transferring a data unit on each segment data lane during a bus read cycle; means for receiving a valid data unit signal from the host system; a buffer, having a plurality of memory locations, for storing each data unit; a data path between the bus interface and the buffer; a network controller, coupled to the buffer and the network, for transferring data units between the network and the buffer; and a data aligner, in the data path, for controlling alignment of each data unit in the data path in response to the valid data unit signal so that the data units having a fixed width are transferred on a subset of the plurality of segment data lanes to form data units of a selected width and a selected alignment, each segment lane in the subset transferring a data unit, without requiring redundant reads of any transferred data unit in the subset.

Claim 37

A method of transferring segments of data between a first data path having N+1 segment lanes D1(n), for n=0 through N, each segment lane D1(n) for transferring a segment of data, and a second data path having N+1 segment lanes D2(n), for n=0 through N, each segment lane D2(n) for transferring a segment of data, comprising step: generating a control signal at a control resource; mapping segments of data between the first data path and the second data path in response to the control signal, the first data path having a selected number and a selected alignment of the segments of data to be transferred, and the second data path having a fixed number of the segments of data to be transferred; and transferring at least a segment of data between the first data path and the second data path in response to the control signal.

Claim 38

A method of transferring segments of data between a first data path having N+1 segment lanes D1(n), for n=0 through N, each segment lane D1(n) for transferring a segment of data, and a second data path having N+1 segment lanes D2(n), for n=0 through N, each segment lane D2(n) for transferring a segment of data, comprising step: generating a control signal at a control resource; mapping segments of data between the first data path and the second data path in response to the control signal, the first data path having a selected number and a selected alignment of the segments of data to be transferred, and the second data path having a fixed number of the segments of data to be transferred; and transferring at least a segment of data between the first data path and the second data path in response to the control signal.

Claim 42

An apparatus for writing segments of data from a host bus to a buffer, the host bus coupled to a first data path having N+1 segment lanes D1(n), for n=0 through N, each segment lane D1(n) for transferring a segment of data, and the buffer coupled to a second data path having N+1 segment lanes D2(n), for n=0 through N, each segment lane D2(n) for transferring a segment of data, comprising: a control resource having a control output for generating a first control signal and a second control signal which map segments of data from the first data path to the second data path without redundant accesses of segments of data to be transferred, the second data path having a fixed number of the segments of data to be transferred, and the first data path having a selected number and a selected alignment of the segments of data to be transferred; a first stage including, a plurality of first stage inputs, coupled to the control resource and the segment lanes D1(n), for n=0 through N, associated with the first data path, for receiving at least a segment of data at a selected first stage input among the plurality of first stage inputs, and a plurality of first stage outputs for supplying the segment of data at a selected first stage output among the plurality of first stage outputs in response to the first control signal; and a second stage including, a plurality of second stage inputs coupled to the control resource and a subset of the plurality of first stage outputs, for receiving the segment of data at a selected second stage input among the plurality of second stage inputs, a plurality of second stage outputs for supplying the segment of data at a selected second stage output among the plurality of second stage outputs in response to the second control signal and coupling the segment of data to the segment lanes associated with the second data path, the second stage capable of queuing and storing segments of data for selectively aligning the segments of data on selected segment lanes of the second data path, wherein the control resource further includes a control input for receiving a segment enable signal for each segment of data on the segment lanes D1(n) to indicate a validity state of the corresponding segment of data, the validity state including a valid state to indicate that the segment lane D1(n) corresponding to the segment enable signal is transferring a valid segment of data, and an invalid state to indicate that the segment lane D1(n) corresponding to the segment enable signal is transferring one of an invalid segment of data and no segment of data, wherein the first control signal includes a rotate signal and the second control signal includes an output enable signal, wherein the first stage includes: a shifter for transferring segments of data from the selected first stage input to the selected first stage output, wherein the plurality of first stage inputs includes a plurality of shifter inputs X1 in (j), for j=0 through N, corresponding to segment lanes D1(n), for n=0 through N, and the plurality of first stage outputs includes a plurality of shifter outputs X1 out (j), for j=0 through N, for transferring segments of data from a selected first stage input X1 in (j) to a selected first stage output X1 out (j) in response to the rotate signal, wherein the second stage includes: a plurality of queuing stores having store inputs R in (k), for k=0 through N-1, coupled to the shifter at the plurality of first stage outputs X1 out (j), for j=0 through N-1, and store outputs R out (k), for k=0 through N-1, for storing the segment of data from the selected shifter outputs in response to a queue enable signal; and a plurality of selectors having selector inputs M in (m), for m=0 through N-1, coupled to the store outputs R out (k), for k=0 through N-1, and shifter outputs X1 out (j), for j=0 through N-1, and selector outputs M out (m), for m=0 through N-1, for supplying a selected segment of data to segment lanes D2(n), for n=0 through N-1, at the second data path in response to the output enable signal, wherein each selector among the plurality of selectors comprises a 2-to-1 multiplexer (MUX), including: a first MUX input coupled to a corresponding store output, a second MUX input coupled to a corresponding shifter output, a MUX control input for receiving the output enable signal and selecting one of the first MUX input and the second MUX input, and a MUX output for transferring the selected segment of data on one of the first MUX input and the second MUX input in response to the output enable signal at the MUX control input, and wherein the control resource generates the rotate signal by determining a data offset value and a current queue value, the data offset value determined by counting the segment lanes D1(n) not transferring segments of data and the current queue value determined by counting the queuing stores storing segments of data, the rotate value equals the current queue value minus the data offset value.

Claim 43

An apparatus for writing segments of data from a host bus to a buffer, the host bus coupled to a first data path having N+1 segment lanes D1(n), for n=0 through N, each segment lane D1(n) for transferring a segment of data, and the buffer coupled to a second data path having N+1 segment lanes D2(n), for n=0 through N, each segment lane D2(n) for transferring a segment of data, comprising: a control resource having a control output for generating a first control signal and a second control signal which map segments of data from the first data path to the second data path without redundant accesses of segments of data to be transferred, the second data path having a fixed number of the segments of data to be transferred, and the first data path having a selected number and a selected alignment of the segments of data to be transferred; a first stage including, a plurality of first stage inputs, coupled to the control resource and the segment lanes D1(n), for n=0 through N, associated with the first data path, for receiving at least a segment of data at a selected first stage input among the plurality of first stage inputs, and a plurality of first stage outputs for supplying the segment of data at a selected first stage output among the plurality of first stage outputs in response to the first control signal; and a second stage including, a plurality of second stage inputs coupled to the control resource and a subset of the plurality of first stage outputs, for receiving the segment of data at a selected second stage input among the plurality of second stage inputs, a plurality of second stage outputs for supplying the segment of data at a selected second stage output among the plurality of second stage outputs in response to the second control signal and coupling the segment of data to the segment lanes associated with the second data path, the second stage capable of queuing and storing segments of data for selectively aligning the segments of data on selected segment lanes of the second data path, wherein the control resource further includes a control input for receiving a segment enable signal for each segment of data on the segment lanes D1(n) to indicate a validity state of the corresponding segment of data, the validity state including a valid state to indicate that the segment lane D1(n) corresponding to the segment enable signal is transferring a valid segment of data, and an invalid state to indicate that the segment lane D1(n) corresponding to the segment enable signal is transferring one of an invalid segment of data and no segment of data, wherein the first control signal includes a rotate signal and the second control signal includes an output enable signal, wherein the first stage includes: a shifter for transferring segments of data from the selected first stage input to the selected first stage output, wherein the plurality of first stage inputs includes a plurality of shifter inputs X1 in (j), for j=0 through N, corresponding to segment lanes D1(n), for n=0 through N, and the plurality of first stage outputs includes a plurality of shifter outputs X1 out (j), for j=0 through N, for transferring segments of data from a selected first stage input X1 in (j) to a selected first stage output X1 out (j) in response to the rotate signal, wherein the second stage includes: a plurality of queuing stores having store inputs R in (k), for k=0 through N-1, coupled to the shifter at the plurality of first stage outputs X1 out (j), for j=0 through N-1, and store outputs R out (k), for k=0 through N-1, for storing the segment of data from the selected shifter outputs in response to a queue enable signal; and a plurality of selectors having selector inputs M in (m), for m=0 through N-1, coupled to the store outputs R out (k), for k=0 through N-1, and shifter outputs X1 out (j), for j=0 through N-1, and selector outputs M out (m), for m=0 through N-1, for supplying a selected segment of data to segment lanes D2(n), for n=0 through N-1, at the second data path in response to the output enable signal, wherein each selector among the plurality of selectors comprises a 2-to-1 multiplexer (MUX), including: a first MUX input coupled to a corresponding store output, a second MUX input coupled to a corresponding shifter output, a MUX control input for receiving the output enable signal and selecting one of the first MUX input and the second MUX input, and a MUX output for transferring the selected segment of data on one of the first MUX input and the second MUX input in response to the output enable signal at the MUX control input, and wherein the control resource generates the rotate signal by determining a data offset value and a current queue value, the data offset value determined by counting the segment lanes D1(n) not transferring segments of data and the current queue value determined by counting the queuing stores storing segments of data, the rotate value equals the current queue value minus the data offset value.

Claim 49

An apparatus for reading segments of data from a buffer to a host bus, the host bus coupled to a first data path having N+1 segment lanes D1(n), for n=0 through N, each segment lane D1(n) for transferring a segment of data, and the buffer coupled to a second data path having N+1 segment lanes D2(n), for n=0 through N, each segment lane D2(n) for transferring a segment of data, comprising: a control resource having a control output for generating a first control signal and a second control signal which map segments of data from the second data path to the first data path without redundant accesses of segments of data to be transferred, the first data path having a selected number and a selected alignment of the segments of data to be transferred, and the second data path having a fixed number of the segments of data to be transferred; a first stage including a plurality of first stage inputs, coupled to the control resource and a subset of the segment lanes D2(n), for n=1 through N, associated with the second data path, for receiving at least a segment of data at a selected first stage input among the plurality of first stage inputs, and a plurality of first stage outputs for supplying the segment of data at a selected first stage output among the plurality of first stage outputs in response to the first control signal; and a second stage including, a plurality of second stage inputs coupled to the control resource and at least a subset of the plurality of first stage outputs and the segment lanes coupled to the plurality of first stage inputs, for receiving the segment of data at a selected second stage input among the plurality of second stage inputs, and a plurality of second stage outputs for supplying the segment of data at a selected second stage output among the plurality of second stage outputs in response to the second control signal and coupling the segment of data to the segment lanes associated with the first data path where the first stage is capable of queuing and storing segments of data for selectively aligning the segments of data on selected segment lanes of the first data path, wherein the control resource further includes a control input for receiving a segment enable signal for each segment of data on the segment lanes D2(n) to indicate a validity state of the corresponding segment of data, the validity state including a valid state to indicate that the segment lane D2(n) corresponding to the segment enable signal is transferring a valid segment of data, and an invalid state to indicate that the segment lane D2(n) corresponding to the segment enable signal is transferring one of an invalid segment of data and no segment of data, wherein the first data path is coupled to a host bus, the second data path is coupled to a buffer, the plurality of first stage inputs is coupled to the second data path, and the plurality of first stage outputs is coupled to the first data path, wherein the first control signal includes a selector enable signal and the second control signal includes a rotate signal, wherein the first stage includes: a plurality of queuing stores having store inputs R in (k), for k=1 through N, coupled to the subset of the segment lanes D2(n), for n=1 through N, and store outputs R out (k), for k=1 through N, for storing the segment of data from the subset of the segment lanes D2(n), for n=1 through N, in response to a queue enable signal; and a plurality of selectors having selector inputs M in (m), for m=1 through N, coupled to the store outputs R out (k), for k=1 through N, and the subset of the segment lanes D2(n), for n=1 through N, and selector outputs M out (m), for m=1 through N, for supplying a selected segment of data to the selector outputs in response to the selector enable signal, wherein the second stage includes: a shifter for transferring segments of data from the selected second stage input to the selected second stage output, wherein the plurality of second stage inputs includes a plurality of shifter inputs X2 in (j), for j=0 through N, coupled to the segment lanes D2(n), for n=0, and the plurality of selectors at the selector outputs M out (m), for m=1 through N, and the plurality of second stage outputs includes a plurality of shifter outputs X2 out (j), for j=0 through N, for transferring segments of data from a selected second stage input X2 in (j) to a selected second stage output X2 out (j) in response to the rotate signal, wherein the selected second stage output X2 out (j) corresponds to the segment lane D1(n) with the lowest n that is enabled for receiving the segment of data, and wherein the control resource generates the rotate signal by determining a data offset value and a read count value, the data offset value determined by counting the segment lanes D2(n) not transferring segments of data and the read count value determined by counting the segment lanes D2(n) transferring segments of data the rotate value equals the data offset value minus the read count value.

Claim 50

An apparatus for reading segments of data from a buffer to a host bus, the host bus coupled to a first data path having N+1 segment lanes D1(n), for n=0 through N, each segment lane D1(n) for transferring a segment of data, and the buffer coupled to a second data path having N+1 segment lanes D2(n), for n=0 through N, each segment lane D2(n) for transferring a segment of data, comprising: a control resource having a control output for generating a first control signal and a second control signal which map segments of data from the second data path to the first data path without redundant accesses of segments of data to be transferred, the first data path having a selected number and a selected alignment of the segments of data to be transferred, and the second data path having a fixed number of the segments of data to be transferred; a first stage including a plurality of first stage inputs, coupled to the control resource and a subset of the segment lanes D2(n), for n=1 through N, associated with the second data path, for receiving at least a segment of data at a selected first stage input among the plurality of first stage inputs, and a plurality of first stage outputs for supplying the segment of data at a selected first stage output among the plurality of first stage outputs in response to the first control signal; and a second stage including, a plurality of second stage inputs coupled to the control resource and at least a subset of the plurality of first stage outputs and the segment lanes coupled to the plurality of first stage inputs, for receiving the segment of data at a selected second stage input among the plurality of second stage inputs, and a plurality of second stage outputs for supplying the segment of data at a selected second stage output among the plurality of second stage outputs in response to the second control signal and coupling the segment of data to the segment lanes associated with the first data path where the first stage is capable of queuing and storing segments of data for selectively aligning the segments of data on selected segment lanes of the first data path, wherein the control resource further includes a control input for receiving a segment enable signal for each segment of data on the segment lanes D2(n) to indicate a validity state of the corresponding segment of data, the validity state including a valid state to indicate that the segment lane D2(n) corresponding to the segment enable signal is transferring a valid segment of data, and an invalid state to indicate that the segment lane D2(n) corresponding to the segment enable signal is transferring one of an invalid segment of data and no segment of data, wherein the first data path is coupled to a host bus, the second data path is coupled to a buffer, the plurality of first stage inputs is coupled to the second data path, and the plurality of first stage outputs is coupled to the first data path, wherein the first control signal includes a selector enable signal and the second control signal includes a rotate signal, wherein the first stage includes: a plurality of queuing stores having store inputs R in (k), for k=1 through N, coupled to the subset of the segment lanes D2(n), for n=1 through N, and store outputs R out (k), for k=1 through N, for storing the segment of data from the subset of the segment lanes D2(n), for n=1 through N, in response to a queue enable signal; and a plurality of selectors having selector inputs M in (m), for m=1 through N, coupled to the store outputs R out (k), for k=1 through N, and the subset of the segment lanes D2(n), for n=1 through N, and selector outputs M out (m), for m=1 through N, for supplying a selected segment of data to the selector outputs in response to the selector enable signal, wherein the second stage includes: a shifter for transferring segments of data from the selected second stage input to the selected second stage output, wherein the plurality of second stage inputs includes a plurality of shifter inputs X2 in (j), for j=0 through N, coupled to the segment lanes D2(n), for n=0, and the plurality of selectors at the selector outputs M out (m), for m=1 through N, and the plurality of second stage outputs includes a plurality of shifter outputs X2 out (j), for j=0 through N, for transferring segments of data from a selected second stage input X2 in (j) to a selected second stage output X2 out (j) in response to the rotate signal, wherein the selected second stage output X2 out (j) corresponds to the segment lane D1(n) with the lowest n that is enabled for receiving the segment of data, and wherein the control resource generates the rotate signal by determining a data offset value and a read count value, the data offset value determined by counting the segment lanes D2(n) not transferring segments of data and the read count value determined by counting the segment lanes D2(n) transferring segments of data the rotate value equals the data offset value minus the read count value.