US4663732A
Expired / Lapsed
US
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Apparatus for storing and retrieving data in predetermined multi-bit quantities containing fewer bits of data than word length quantities
Assignee: KLA Corp
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Filing: 1984-02-22
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Granted: 1987-05-05
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Expires: 2004-02-22
Abstract
Abstract An apparatus for storing and retrieving data in predetermined multi-bit length quantities containing fewer bits of data than word length quantities, including a memory for storing word length quantities at particular storage sites, a first buffer for selectively receiving data bits contained in a first predetermined portion of a word length quantity of data stored at a particular address within the memory, a second buffer for selectively receiving data bits contained in a second predetermined portion of the word length quantity of data stored at the particular address, a third buffer for alternatively receiving data bits contained in the second predetermined portion of the word length quantity of data stored at the particular address, a data bit generator for generating a null signal in the form of a predetermined number of data bits, a data bus having a first data transfer part and a second data transfer part connected to the memory, a CPU for causing the respective first and second portions of data and the null signal to be transferred from the memory and/or the data bit generator through the first, second, or third buffers to the data bus in accordance with one of the three following alternatives: (a) the first predetermined portion is input to the first part of the data bus, and the second predetermined portion is input to the second part of the data bus; or (b) the first predetermined portion is input to the first part of the data bus, and the null signal is input to the second part of the data bus; or (c) the second predetermined portion is input to the second part of the data bus, and the null signal is input to the second part of the data bus.
Inventors
- 👤 C. Michael Robinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:07
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/12; G06; G06F; G06F12/00; G06F12/02; G06F12/04; G09G5/36
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
413 words
An apparatus for storing and retrieving data in predetermined multi-bit length quantities containing fewer bits of data than word length quantities wherein said predetermined multi-bit length is a predetermined submultiple of said word length, comprising: memory means for storing word length quantities of data at storage sites having particular addresses whereby each word length quantity of data includes a multiple of said predetermined multi-bit length quantities of data; a first buffer means for selectively receiving data bits of said predetermined multi-bit length contained in a first predetermined portion of a word length quantity of data stored at a particular address within said memory means; a second buffer means for selectively receiving data bits of said predetermined multi-bit length contained in a second predetermined portion of said word length quantity of data stored at said particular address within said memory means; a third buffer means for alternately receiving data bits of said predetermined multi-bit length contained in said second predetermined portion of said word length quantity of data stored at said particular address; data bit means for generating a null signal in the form of a predetermined number of data bits of said predetermined multi-bit length; data bus means having a first data transfer part and a second data transfer part connected to the memory means; a CPU means connected to the data bus means, said CPU means causing the respective first and second portions of data and said null signal to be transferred from said memory means and/or said data bit means through said first, second and third buffer means to said data bus means in accordance with one of the following alternatives: (a) said first predetermined portion to be input to said first part of said data bus means and said second predetermined portion to be input to said second part of said data bus means when a word length quantity of data is retrieved from said memory means; (b) said first predetermined portion to be input to said first part of said data bus means and said null signal to be input to said second part of said data bus means when data of said predetermined multi-bit length is retrieved from said memory means; and (c) said second predetermined portion to be input to said first part of said data bus means and said null signal to be input to said second part of said data bus means when data of said predetermined multi-bit length is retrieved from said memory means.
Claim 2
Independent Claim
413 words
An apparatus for storing and retrieving data in predetermined multi-bit length quantities containing fewer bits of data than word length quantities wherein said predetermined multi-bit length is a predetermined submultiple of said word length, comprising: memory means for storing word length quantities of data at storage sites having particular addresses whereby each word length quantity of data includes a multiple of said predetermined multi-bit length quantities of data; a first buffer means for selectively receiving data bits of said predetermined multi-bit length contained in a first predetermined portion of a word length quantity of data stored at a particular address within said memory means; a second buffer means for selectively receiving data bits of said predetermined multi-bit length contained in a second predetermined portion of said word length quantity of data stored at said particular address within said memory means; a third buffer means for alternately receiving data bits of said predetermined multi-bit length contained in said second predetermined portion of said word length quantity of data stored at said particular address; data bit means for generating a null signal in the form of a predetermined number of data bits of said predetermined multi-bit length; data bus means having a first data transfer part and a second data transfer part connected to the memory means; a CPU means connected to the data bus means, said CPU means causing the respective first and second portions of data and said null signal to be transferred from said memory means and/or said data bit means through said first, second and third buffer means to said data bus means in accordance with one of the following alternatives: (a) said first predetermined portion to be input to said first part of said data bus means and said second predetermined portion to be input to said second part of said data bus means when a word length quantity of data is retrieved from said memory means; (b) said first predetermined portion to be input to said first part of said data bus means and said null signal to be input to said second part of said data bus means when data of said predetermined multi-bit length is retrieved from said memory means; and (c) said second predetermined portion to be input to said first part of said data bus means and said null signal to be input to said second part of said data bus means when data of said predetermined multi-bit length is retrieved from said memory means.
Claim 3
Dependent Claim
63 words
The apparatus of claim 1 wherein said memory means is a RAM array organized to store n bits of data per addressable storage site, said first part of said data bus is organized to transmit m bits of data, where m is less than n, and said second part of said data bus is organized to transmit p bits of data, where m+p=n.
Claim 4
Dependent Claim
22 words
The apparatus of claim 2 wherein said first buffer means, said second buffer means, and said third buffer means are tri-state buffers.
Claim 5
Dependent Claim
57 words
The apparatus of claim 3 wherein the first and second tri state buffers can be enabled to transfer word length quantities of data onto the system data bus, and said first and third tri-state buffers can be alternately enabled to transfer predetermined length portions of data onto the first data transfer part of the system data bus.
Claim 6
Dependent Claim
50 words
The apparatus of claim 1 wherein said first predetermined portion and said second predetermined portion are each comprised of no more than m bits of data and said data bus accommodates the transfer of at least n bits of data, where n is an integer and a multiple of m.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-04 | 1990-11-03 | 1991-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-04 | 1994-11-03 | 1995-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-04 | 1998-11-03 | 1999-05-05 | $7700.00 | Window Closed / Lapsed |