Logic support chip for AT-type computer with improved bus architecture

Claim 2

A logic support chip for use in combination with (a) an external processor having local address and data buses, and (b) a pair of external 8-bit bidirectional buffers, referred to as the external buffers, to implement an AT-compatible microcomputer system, the microcomputer system being characterized by a low-impedance 16-bit data bus, designated the SD-bus, and a high-impedance data bus, designated the XD-bus, the chip comprising: a first set of 16 pins adapted to be coupled to the external processor's local data bus, said first set of pins defining a first data bus interface; a second set of 16 pins adapted to be coupled to the external buffers via an external 16-bit XD-bus, said second set of pins defining a second data bus interface; an internal 16-bit data bus coupled between said first and second sets of pins; said internal data bus and the external XD-bus each having high-order and low-order 8-bit segments; said first and second data bus interfaces being the chip's only data bus interfaces; a third set of pins, including first and second direction control pins adapted to be coupled to direction control inputs on the external buffers; swapper means, coupled between said high-order and low-order segments of said internal data bus and responsive to swapper control signals, for directing data on either segment of said internal data bus onto the other segment of said internal data bus; and data path control means, coupled to said swapper means and said first and second direction control pins, for generating said swapper control signals and a pair of direction control signals, said direction control signals being provided to said direction control pins and being adapted to control the respective directions of the external buffers.

Claim 3

The chip of claim 1 wherein the chip has a total number of pins that is no more than 160.

Claim 4

The chip of claim 1 wherein the chip has a total number of pins that is no more than 160.

Claim 5

An AT-compatible computer comprising: a microprocessor having local address and data bus pins; an external 16-bit XD-bus, said external XD-bus having high-order and low-order 8-bit segments; an external 16-bit SD-bus, said external SD-bus having high-order and low-order 8-bit segments; said XD-bus and said SD-bus being characterized by respective impedances, the impedance of said XD-bus being significantly higher than the impedance of said SD-bus; a first bidirectional buffer coupling the high-order segments of said XD-bus and said SD-bus; a second bidirectional buffer coupling the low-order segments of said XD-bus and said SD-bus; each buffer having a respective direction control input; a single-chip support circuit, referred to as the chip, the chip having a first set of address pins, a first set of data pins, a second set of data pins, and a set of direction control pins; an internal address bus on the chip; an internal data bus on the chip, said internal data bus having high-order and low-order 8-bit segments; means, located on the chip, for interfacing said internal address bus to said local address bus at said first set of address pins; means, located on the chip, for interfacing said internal data bus to said local data bus at said first set of data pins; means, located on the chip, for interfacing said internal data bus to said XD-bus at said second set of data pins; a swapper circuit on the chip, interposed between the high-order and low-order segments of said internal data bus, said swapper being operable, in response to swapper control signals, to drive data appearing on one of the 8-bit segments of said internal data bus onto the other 8-bit segments of said internal data bus; and a data path control circuit on the chip, coupled to said swapper circuit and to said direction control pins, for providing (a) direction control signals to said first and second bidirectional buffers, and (b) internal control signals to said swapper circuit.

Claim 6

An AT-compatible computer comprising: a microprocessor having local address and data bus pins; an external 16-bit XD-bus, said external XD-bus having high-order and low-order 8-bit segments; an external 16-bit SD-bus, said external SD-bus having high-order and low-order 8-bit segments; said XD-bus and said SD-bus being characterized by respective impedances, the impedance of said XD-bus being significantly higher than the impedance of said SD-bus; a first bidirectional buffer coupling the high-order segments of said XD-bus and said SD-bus; a second bidirectional buffer coupling the low-order segments of said XD-bus and said SD-bus; each buffer having a respective direction control input; a single-chip support circuit, referred to as the chip, the chip having a first set of address pins, a first set of data pins, a second set of data pins, and a set of direction control pins; an internal address bus on the chip; an internal data bus on the chip, said internal data bus having high-order and low-order 8-bit segments; means, located on the chip, for interfacing said internal address bus to said local address bus at said first set of address pins; means, located on the chip, for interfacing said internal data bus to said local data bus at said first set of data pins; means, located on the chip, for interfacing said internal data bus to said XD-bus at said second set of data pins; a swapper circuit on the chip, interposed between the high-order and low-order segments of said internal data bus, said swapper being operable, in response to swapper control signals, to drive data appearing on one of the 8-bit segments of said internal data bus onto the other 8-bit segments of said internal data bus; and a data path control circuit on the chip, coupled to said swapper circuit and to said direction control pins, for providing (a) direction control signals to said first and second bidirectional buffers, and (b) internal control signals to said swapper circuit.

Claim 7

The computer of claim 4 wherein said microprocessor is an 80286.

Claim 8

The computer of claim 4 wherein said data path control means is able to provide signals to said first and second bidirectional buffers and said swapper to permit data on one segment of said external XD-bus to be communicated onto the corresponding segment of said XD-bus, onto the corresponding segment of said internal data bus, through said swapper, onto the other segment of said internal data bus, onto the other segment of said XD-bus, and onto the other segment of said SD-bus.

Claim 9

The computer of claim 4 wherein said support chip has a total of no more than 160 pins.

Claim 10

A logic support chip for use in combination with (a) an external processor having local address and data buses, and (b) a pair of external 8-bit bidirectional buffers, referred to as the external buffers, to implement an AT-compatible microcomputer system, the microcomputer system being characterized by a 16-bit data bus, designated the SD-bus, and a data bus, designated the XD-bus, the SD-bus and the XD-bus being characterized by respective drive current requirements, the drive current requirement for the SD-bus being greater than that for the XD-bus, the chip comprising: a first set of 16 pins adapted to be coupled to the external processor's local data bus, said first set of pins defining a first data bus interface; a second set of 16 pins adapted to be coupled to the external buffers via an external 16-bit XD-bus, said second set of pins defining a second data bus interface; said first and second data bus interfaces being the chip's only data bus interfaces; a third set of pins, including first and second direction control pins adapted to be coupled to direction control inputs on the external buffers; a fourth set of pins adapted to be coupled to the processor's local address bus; an internal 16-bit data bus; first and second sets of transceivers coupling said internal data bus to said first and second sets of pins, respectively, said second set of transceivers having respective driver portions capable of meeting the drive current requirement for the XD-bus but not that for the SD-bus; an internal address bus coupled to said fourth set of pins; said internal data bus and the external XD-bus each having high-order and low-order 8-bit segments; a data swapper coupled between said high-order and low-order segments of said internal data bus and responsive to swapper control signals, operable to direct data on either segment of said internal data bus onto the other segment of said internal data bus; means, coupled to at least a portion of said internal address bus, for generating a set of I/O decode signals; means, coupled to said data swapper for generating said swapper control signals; and means, responsive to at least some of said I/O decode signals, for generating a pair of direction control signals, said direction control signals being provided to said direction control pins and being adapted to control the respective directions of the external buffers.

Claim 11

A logic support chip for use in combination with (a) an external processor having local address and data buses, and (b) a pair of external 8-bit bidirectional buffers, referred to as the external buffers, to implement an AT-compatible microcomputer system, the microcomputer system being characterized by a 16-bit data bus, designated the SD-bus, and a data bus, designated the XD-bus, the SD-bus and the XD-bus being characterized by respective drive current requirements, the drive current requirement for the SD-bus being greater than that for the XD-bus, the chip comprising: a first set of 16 pins adapted to be coupled to the external processor's local data bus, said first set of pins defining a first data bus interface; a second set of 16 pins adapted to be coupled to the external buffers via an external 16-bit XD-bus, said second set of pins defining a second data bus interface; said first and second data bus interfaces being the chip's only data bus interfaces; a third set of pins, including first and second direction control pins adapted to be coupled to direction control inputs on the external buffers; a fourth set of pins adapted to be coupled to the processor's local address bus; an internal 16-bit data bus; first and second sets of transceivers coupling said internal data bus to said first and second sets of pins, respectively, said second set of transceivers having respective driver portions capable of meeting the drive current requirement for the XD-bus but not that for the SD-bus; an internal address bus coupled to said fourth set of pins; said internal data bus and the external XD-bus each having high-order and low-order 8-bit segments; a data swapper coupled between said high-order and low-order segments of said internal data bus and responsive to swapper control signals, operable to direct data on either segment of said internal data bus onto the other segment of said internal data bus; means, coupled to at least a portion of said internal address bus, for generating a set of I/O decode signals; means, coupled to said data swapper for generating said swapper control signals; and means, responsive to at least some of said I/O decode signals, for generating a pair of direction control signals, said direction control signals being provided to said direction control pins and being adapted to control the respective directions of the external buffers.

Claim 12

An AT-compatible computer comprising: a microprocessor having local address and data bus pins; an external 16-bit XD-bus, said external XD-bus having high-order and low-order 8-bit segments; an external 16-bit SD-bus, said external SD-bus having high-order and low-order 8-bit segments; said SD-bus and said XD-bus being characterized by respective drive current requirements, the drive current requirement for said SD-bus being greater than that for said SD-bus; a first bidirectional buffer coupling the high-order segments of said XD-bus and said SD-bus; a second bidirectional buffer coupling the low-order segments of said XD-bus and said SD-bus; each buffer having a respective direction control input; a single-chip support circuit, referred to as the chip, the chip having a first set of address pins, a first set of data pins, a second set of data pins, and a set of direction control pins; an internal address bus on the chip; an internal data bus on the chip, said internal data bus having high-order and low-order 8-bit segments; a set of address transceivers, located on the chip, for interfacing said internal address bus to said local address bus at said first set of address pins; a first set of data transceivers, located on the chip, for interfacing said internal data bus to said local data bus at said first set of data pins; a second set of data transceivers, located on the chip, for interfacing said internal data bus to said XD-bus at said second set of data pins; a swapper circuit on the chip, interposed between the high-order and low-order segments of said internal data bus, said swapper being operable, in response to swapper control signals, to drive data appearing on one of the 8-bit segments of said internal data bus onto the other 8-bit segment of said internal data bus; a data path control circuit on the chip, for providing (a) direction control signals to said first and second bidirectional buffers, and (b) internal swapper control signals to said swapper circuit.

Claim 13

An AT-compatible computer comprising: a microprocessor having local address and data bus pins; an external 16-bit XD-bus, said external XD-bus having high-order and low-order 8-bit segments; an external 16-bit SD-bus, said external SD-bus having high-order and low-order 8-bit segments; said SD-bus and said XD-bus being characterized by respective drive current requirements, the drive current requirement for said SD-bus being greater than that for said SD-bus; a first bidirectional buffer coupling the high-order segments of said XD-bus and said SD-bus; a second bidirectional buffer coupling the low-order segments of said XD-bus and said SD-bus; each buffer having a respective direction control input; a single-chip support circuit, referred to as the chip, the chip having a first set of address pins, a first set of data pins, a second set of data pins, and a set of direction control pins; an internal address bus on the chip; an internal data bus on the chip, said internal data bus having high-order and low-order 8-bit segments; a set of address transceivers, located on the chip, for interfacing said internal address bus to said local address bus at said first set of address pins; a first set of data transceivers, located on the chip, for interfacing said internal data bus to said local data bus at said first set of data pins; a second set of data transceivers, located on the chip, for interfacing said internal data bus to said XD-bus at said second set of data pins; a swapper circuit on the chip, interposed between the high-order and low-order segments of said internal data bus, said swapper being operable, in response to swapper control signals, to drive data appearing on one of the 8-bit segments of said internal data bus onto the other 8-bit segment of said internal data bus; a data path control circuit on the chip, for providing (a) direction control signals to said first and second bidirectional buffers, and (b) internal swapper control signals to said swapper circuit.

Claim 14

The computer of claim 9 wherein said microprocessor is an 80286.

Claim 15

The computer of claim 9 wherein said microprocessor is an 80286 and said chip has a total number of pins that is no more than 160.