Patent US5515384A successfully refreshed from Google Patents.
US5515384A
Expired / Lapsed
US
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Method and system of fault diagnosis of application specific electronic circuits
Assignee: Cadence Design Systems Inc
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Filing: 1994-03-01
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Granted: 1996-05-07
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Expires: 2014-03-01
Abstract
Abstract A complete fail signature for an integrated circuit is compared to at least one predicted fail signature generated using a hardware fault simulator to generate fault candidates for the integrated circuit representing the most likely faults present within the tested circuit or device. The complete fail signature may be generated by obtaining physical test data for the integrated circuit derived by testing the integrated circuit using test vectors and comparing the results of the testing with the test results of a flawless integrated circuit to generate a fail signature. Also, the complete fail signature may be generated by compiling the logic of the integrated circuit into binary language suitable for simulation in a hardware fault simulator and compiling the test vectors into binary language suitable for simulation in the hardware fault simulator. The logic function of the integrated circuit may be simulated on the hardware fault simulator and the test vectors applied to the hardware fault simulator to determine an expected output of the integrated circuit. The expected output may be combined with the fail signature to generate a complete fail signature representative of a complete output pattern of the integrated circuit.
Inventors
- 👤 Edward E. Horton, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:17
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
47 words
A method for diagnosing faults in an application specific integrated circuit comprising: comparing a complete fail signature for an integrated circuit to at least one predicted fail signature generated using a hardware fault simulator; and compiling fault candidates in said integrated circuit based upon said comparing step.
Claim 2
Independent Claim
47 words
A method for diagnosing faults in an application specific integrated circuit comprising: comparing a complete fail signature for an integrated circuit to at least one predicted fail signature generated using a hardware fault simulator; and compiling fault candidates in said integrated circuit based upon said comparing step.
Claim 3
Dependent Claim
39 words
The method of claim 1 wherein an expected output of a flawless version of said integrated circuit is combined with a fail signature to generate said complete fail signature representative of a complete output pattern of said integrated circuit.
Claim 4
Dependent Claim
21 words
The method of claim 1 further comprising generating said complete fail signature by obtaining physical test data for said integrated circuit.
Claim 5
Dependent Claim
54 words
The method of claim 3 wherein obtaining physical test data for an integrated circuit to generate a complete fail signature for said integrated circuit is accomplished by: testing said integrated circuit using test vectors; and comparing results of said testing with test results of a similar flawless integrated circuit to generate said fail signature.
Claim 6
Dependent Claim
57 words
The method of claim 3 wherein obtaining physical test data for an integrated circuit to generate a complete fail signature further comprises: compiling the logic of said flawless integrated circuit into binary language suitable for simulation in a hardware fault simulator; and compiling said test vectors into binary language suitable for simulation in a hardware fault simulator.
Claim 7
Dependent Claim
40 words
The method of claim 5 wherein said expected output of said integrated circuit is obtained by simulating the logic function of said flawless integrated circuit on said hardware fault simulator and applying said test vectors to said hardware fault simulator.
Claim 8
Dependent Claim
19 words
The method of claim 3 or 5 further comprising generating a list of possible faults in said integrated circuit.
Claim 9
Dependent Claim
31 words
The method of claim 7 wherein generating said list of possible faults comprising tracing a cone of logic in reverse from one or more faulty output pins of said fail signature.
Claim 10
Dependent Claim
49 words
The method of claim 7 further comprising simulating each possible fault of said list of possible faults on said hardware fault simulator to generate at least one or more predicted fail signature, each predicted fail signature corresponding to the predicted output of said integrated circuit having said simulated fault.
Claim 11
Dependent Claim
11 words
The method of claim 9 further comprising grading said fault candidates.
Claim 12
Dependent Claim
11 words
The method of claim 9 further comprising reporting said fault candidates.
Claim 13
Dependent Claim
27 words
The method of claim 1 wherein comparing said complete fail signature is for an integrated circuit designed without the use of level sensitive scan design circuitry techniques.
Claim 14
Independent Claim
94 words
A method of diagnosing faults in an application specific integrated circuit comprising: combining an expected output of an integrated circuit with a fail signature for said integrated circuit to create a complete fail signature for said integrated circuit; simulating possible faults on a hardware fault simulator to create at least one predicted fail signature, each predicted fail signature corresponding to the predicted output of said integrated circuit having a particular fault therein; comparing each predicted fail signature with said complete fail signature to generate a list of possible fault candidates in said integrated circuit.
Claim 15
Independent Claim
94 words
A method of diagnosing faults in an application specific integrated circuit comprising: combining an expected output of an integrated circuit with a fail signature for said integrated circuit to create a complete fail signature for said integrated circuit; simulating possible faults on a hardware fault simulator to create at least one predicted fail signature, each predicted fail signature corresponding to the predicted output of said integrated circuit having a particular fault therein; comparing each predicted fail signature with said complete fail signature to generate a list of possible fault candidates in said integrated circuit.
Claim 16
Independent Claim
45 words
A system for diagnosing faults in an application specific integrated circuit comprising: means for comparing a complete fail signature for an integrated circuit to at least one predicted fail signature; and means for compiling fault candidates in said integrated circuit based upon said comparing step.
Claim 17
Independent Claim
45 words
A system for diagnosing faults in an application specific integrated circuit comprising: means for comparing a complete fail signature for an integrated circuit to at least one predicted fail signature; and means for compiling fault candidates in said integrated circuit based upon said comparing step.
Claim 18
Dependent Claim
23 words
The system of claim 14 further comprising means for generating said complete fail signature by obtaining physical test data for said integrated circuit.
Claim 19
Dependent Claim
38 words
The system of claim 15 further comprising: means for testing an integrated circuit using test vectors; and means for comparing results of said testing with test results of a similar flawless integrated circuit to generate a fail signature.
Claim 20
Dependent Claim
44 words
The system of claim 16 further comprising: means for compiling the logic of said integrated circuit into binary language suitable for simulation in a hardware simulator; and means for compiling said test vectors into binary language suitable for simulation in a hardware fault simulator.
Claim 21
Dependent Claim
17 words
The system of claim 16 further comprising means for simulating the logic function of said integrated circuit.
Claim 22
Dependent Claim
21 words
The system of claim 18 further comprising means for applying test vectors to determine an expected output of said integrated circuit.
Claim 23
Dependent Claim
22 words
The system of claim 19 wherein said means for simulating the logic function of said integrated circuit comprises a hardware fault simulator.
Claim 24
Dependent Claim
37 words
The system of claim 20 further comprising means for combining the expected output of said integrated circuit with said fail signature to generate a complete fail signature representative of a complete output pattern of said integrated circuit.
Claim 25
Dependent Claim
19 words
The system of claim 21 further comprising means for generating a list of possible faults in said integrated circuit.
Claim 26
Dependent Claim
36 words
The system of claim 22 wherein said means for generating said list of possible faults comprises means for tracing a cone of logic in reverse from one or more faulty output pins of said fail signature.
Claim 27
Dependent Claim
13 words
The system of claim 22 further comprising means for grading said fault candidates.
Claim 28
Dependent Claim
13 words
The system of claim 22 further comprising means for reporting said fault candidates.
Claim 29
Dependent Claim
41 words
The system of claim 14 wherein said means for comparing said complete fail signature for an integrated circuit is capable of comparing the complete fail signature of an integrated circuit designed without the use of level sensitive scan design circuitry techniques.
Claim 30
Independent Claim
94 words
A system of diagnosing faults in an application specific integrated circuit comprising: means for combining an expected output of an integrated circuit with a fail signature for said integrated circuit to create a complete fail signature for said integrated circuit; means for simulating possible faults to create at least one predicted fail signature, each predicted fail signature corresponding to the predicted output of said integrated circuit having a particular fault therein; means for comparing each predicted fail signature with said complete fail signature to generate a list of possible faults in said integrated circuit.
Claim 31
Independent Claim
94 words
A system of diagnosing faults in an application specific integrated circuit comprising: means for combining an expected output of an integrated circuit with a fail signature for said integrated circuit to create a complete fail signature for said integrated circuit; means for simulating possible faults to create at least one predicted fail signature, each predicted fail signature corresponding to the predicted output of said integrated circuit having a particular fault therein; means for comparing each predicted fail signature with said complete fail signature to generate a list of possible faults in said integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-07 | 1999-11-06 | 2000-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-07 | 2003-11-06 | 2004-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-07 | 2007-11-06 | 2008-05-07 | $7700.00 | Window Closed / Lapsed |