US5177440A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Testing of integrated circuits using clock bursts
Assignee: LSI Corp
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Filing: 1991-07-11
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Granted: 1993-01-05
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Expires: 2011-07-11
Abstract
Abstract A method of testing integrated circuits at high operating speeds is provided which is applicable to sequential logic circuits such as ASICs. A general purpose ASIC tester applies test vectors to the integrated circuit under test. The logic input signals are held unchanged and a series of high speed clock signals (a clock burst) are applied to the clock terminals of the integrated circuit. These clock signals are provided at the speed at which it is desired to test the integrated circuit. Then the output terminals are observed to determined if the device is in the expected state (as determined by simulation) after the clock burst. The process is repeated until no further output terminals change state, and then the device may be reinitialized and another series of state changes initiated. Thus every path in the circuit may be tested at high speed by a conventional low speed tester.
Inventors
- 👤 Robert M. Walker, III
- 👤 Dick L. Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:27
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193; G01R31/31937
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
167 words
A device for testing an electronic circuit having a plurality of sequential logic elements comprising: means for applying test signals to logic input terminals of the electronic circuit; a simulator for determining expected output signals of the electronic circuit as a result of the applied test signals so as to determine that the output signals are in a known state; means for observing output signals at output terminals of the circuit during a period when no clock signals are applied for the purpose of testing the circuit; a clock signal generator external to the circuit for applying at least two clock signals to a clock input terminal of the circuit at a predetermined frequency at least approximately equal to a specified operating speed of the circuit; and means for comparing the observed output signals at the output terminals to the expected output signals so as to determine that the circuit functions at the predetermined frequency for substantially all the elements of the plurality of sequential logic elements.
Claim 2
Independent Claim
167 words
A device for testing an electronic circuit having a plurality of sequential logic elements comprising: means for applying test signals to logic input terminals of the electronic circuit; a simulator for determining expected output signals of the electronic circuit as a result of the applied test signals so as to determine that the output signals are in a known state; means for observing output signals at output terminals of the circuit during a period when no clock signals are applied for the purpose of testing the circuit; a clock signal generator external to the circuit for applying at least two clock signals to a clock input terminal of the circuit at a predetermined frequency at least approximately equal to a specified operating speed of the circuit; and means for comparing the observed output signals at the output terminals to the expected output signals so as to determine that the circuit functions at the predetermined frequency for substantially all the elements of the plurality of sequential logic elements.
Claim 3
Dependent Claim
46 words
The device of claim 1, wherein the simulator simulates operation of the circuit using a computer program to determine the expected output signals as a result of the test signals applied to the logic input terminals and the clock signals applied to the clock input terminal.
Claim 4
Dependent Claim
42 words
The device of claim 2, wherein the simulator includes means for forming a database including a linked list, each element of which list includes one of the test signals, an associated expected output signal, and a corresponding internal state of the circuit.
Claim 5
Dependent Claim
16 words
The device of claim 2 wherein the simulator includes a list of the expected output signals.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-01-05 | 1996-07-06 | 1997-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-01-05 | 2000-07-06 | 2001-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-01-05 | 2004-07-06 | 2005-01-05 | $7700.00 | Window Closed / Lapsed |