Dual voltage level shifted, cascoded current mirror

Claim 2

A current mirror circuit comprising: an input terminal; an output terminal; a common voltage terminal; first and second transistors having sources commonly connected to said common voltage terminal, gates commonly connected to each other, and drains; third and fourth transistors having sources respectively connected to said drains of said first and second transistors, gates commonly connected to each other, and drains respectively connected to said input and output terminals; voltage level shifting circuitry comprising a fifth transistor having a gate connected to said input terminal and a source connected to said common connection of said third and fourth transistor gates, and a current source connected to establish current through said fifth transistor, for applying a forward biasing voltage at said common connection of said third and fourth transistor gates equal to an input voltage applied at said input terminal, shifted by a voltage differential between said fifth transistor gate and source; and gate driving circuitry connected to said commonly connected gates of said first and second transistor gates, for applying a forward biasing voltage at said common connection of said first and second transistor gates.

Claim 3

The circuit of claim 1, further comprising an applied voltage terminal; said fifth transistor having a drain connected to said applied voltage terminal; and said current source comprising a sixth transistor having a drain connected to said fifth transistor source, and a source connected to said common voltage terminal.

Claim 4

The circuit of claim 2, wherein said sixth transistor has a gate connected to said common connection of said first and second transistor gates.

Claim 5

The circuit of claim 2, wherein said gate driving circuitry comprises second voltage level shifting circuitry connected between said applied voltage terminal and said common voltage level terminal.

Claim 6

The circuit of claim 1, wherein said gate driving circuitry comprises a first gate driving circuitry transistor having a gate connected to said input terminal and a source connected to said common connection of said first and second transistor gates, and a second gate driving circuitry transistor having a gate connected to said common connection of said first and second transistor gates, a drain connected to its gate, and a source connected to said common voltage terminal.

Claim 7

A current mirror circuit comprising: an input terminal; an output terminal; an applied voltage terminal; a common voltage terminal; first and second transistors having sources commonly connected to said common voltage terminal, gates commonly connected to each other, and drains; third and fourth transistors having sources respectively connected to said drains of said first and second transistors gates commonly connected to each other, and drains respectively connected to said input and output terminals; first voltage level shifting circuitry comprising a fifth transistor having a gate connected to said input terminal, a drain connected to said applied voltage terminal, and a source connected to said common connection of said third and fourth transistor gates; and a sixth transistor having a gate connected to said common connection of said first and second transistor gates, a drain connected to said source of said fifth transistor, and a source connected to said common voltage terminal; and second voltage level shifting circuitry connected between said applied voltage terminal and said common voltage terminal, for applying a forward biasing voltage at said common connection of said first and second transistor gates.

Claim 8

A current mirror circuit comprising: an input terminal; an output terminal; an applied voltage terminal; a common voltage terminal; first and second transistors having sources commonly connected to said common voltage terminal, gates commonly connected to each other, and drains; third and fourth transistors having sources respectively connected to said drains of said first and second transistors gates commonly connected to each other, and drains respectively connected to said input and output terminals; first voltage level shifting circuitry comprising a fifth transistor having a gate connected to said input terminal, a drain connected to said applied voltage terminal, and a source connected to said common connection of said third and fourth transistor gates; and a sixth transistor having a gate connected to said common connection of said first and second transistor gates, a drain connected to said source of said fifth transistor, and a source connected to said common voltage terminal; and second voltage level shifting circuitry connected between said applied voltage terminal and said common voltage terminal, for applying a forward biasing voltage at said common connection of said first and second transistor gates.

Claim 9

The circuit of claim 6, wherein said second voltage level shifter circuitry comprises seventh and eighth transistors, series-connected between said applied voltage terminal and said common voltage terminal.

Claim 10

The circuit of claim 7, wherein said seventh transistor has a gate connected to said input terminal, a drain connected to said applied voltage terminal, and a source connected to said common connection of said first and second transistor gates; and wherein said eighth transistor has a gate connected to said common connection of said first and second transistor gates, a drain connected to said source of said seventh transistor, and a source connected to said common voltage terminal.

Claim 11

The circuit of claim 8, wherein said eighth transistor is diode-connected with its gate connected to its drain.

Claim 12

The circuit of claim 9, wherein said transistors are all MOS transistors formed on a same integrated circuit.

Claim 13

The circuit of claim 10, wherein said transistors are all N-channel MOS transistors and said common voltage terminal is a ground terminal.

Claim 14

A current mirror circuit comprising: an input terminal; an output terminal; a common voltage terminal; first and second transistors connected in current mirrored fashion, with gates of said first and second transistors connected to each other, and with sources of said first and second transistors commonly connected to said common voltage terminal; third and fourth transistors connected in cascoded fashion, respectively in series with said first and second transistors, with gates of said third and fourth transistors connected to each other, with drains of said third and fourth transistors respectively connected to said input and output terminals, and with sources of said third and fourth transistors respectively connected to drains of said first and second transistors; first voltage level shifting means connected to said third and fourth transistor gate connection, including a fifth transistor having a gate connected to said input terminal and a source connected to said gates of said third and fourth transistors; and a sixth transistor having a drain connected to said source of said fifth transistor, a gate connected to said gates of said first and second transistors, and a source connected to said common voltage terminal; second voltage level shifting means connected to said first and second transistor gate connection, including a seventh transistor having a gate connected to said input terminal and a source connected to said gates of said first and second transistors; and an eighth transistor having a drain connected to said source of said seventh transistor, a gate connected to said gates of said first and second transistors, and a source connected to said common voltage terminal; and means for biasing said eighth transistor into saturation.

Claim 15

A current mirror circuit comprising: an input terminal; an output terminal; a common voltage terminal; first and second transistors connected in current mirrored fashion, with gates of said first and second transistors connected to each other, and with sources of said first and second transistors commonly connected to said common voltage terminal; third and fourth transistors connected in cascoded fashion, respectively in series with said first and second transistors, with gates of said third and fourth transistors connected to each other, with drains of said third and fourth transistors respectively connected to said input and output terminals, and with sources of said third and fourth transistors respectively connected to drains of said first and second transistors; first voltage level shifting means connected to said third and fourth transistor gate connection, including a fifth transistor having a gate connected to said input terminal and a source connected to said gates of said third and fourth transistors; and a sixth transistor having a drain connected to said source of said fifth transistor, a gate connected to said gates of said first and second transistors, and a source connected to said common voltage terminal; second voltage level shifting means connected to said first and second transistor gate connection, including a seventh transistor having a gate connected to said input terminal and a source connected to said gates of said first and second transistors; and an eighth transistor having a drain connected to said source of said seventh transistor, a gate connected to said gates of said first and second transistors, and a source connected to said common voltage terminal; and means for biasing said eighth transistor into saturation.

Claim 16

The circuit of claim 12, further comprising an applied voltage terminal; and wherein said fifth and seventh transistors have drains commonly connected to said applied voltage terminal.

Claim 17

The circuit of claim 13, wherein said means for biasing said eighth transistor into saturation comprises said drain and gate of said eighth transistor being connected together.

Claim 18

A current mirror circuit, comprising: an input terminal; an output terminal; an applied voltage terminal; a common voltage terminal; a first pair of transistors connected in parallel, current mirroring configuration to said common voltage terminal; a second pair of transistors connected in parallel cascoded configuration between respective ones of said input and output terminals and respective ones of said first pair of transistors; first voltage level shifting means connected between said applied voltage terminal and said second pair of transistors to control forward biasing of said second pair of transistors; said first voltage level shifting means comprising a third pair of transistors connected in series between said applied voltage terminal and said common voltage terminal; second voltage level shifting means connected between said applied voltage terminal and said first pair of transistors to control forward biasing of said first pair of transistors; said second voltage level shifting means comprising a fourth pair of transistors connected in series between said applied voltage terminal and said common voltage terminal; wherein each of said transistors has first, second and third terminals; said second and third terminals defining a current flow and said first terminal defining a contact for applying a voltage for controlling current flow through said current flow path; said first pair of transistors comprises first and second transistors having commonly connected first and second terminals; said second pair of transistors comprises third and fourth transistors having first terminals connected together, second terminals respectively connected to said third terminals of said first and second transistors and third terminals respectively connected to said input and output terminals; and said third pair of transistors comprises fifth and sixth transistors; said fifth transistor having its first terminal connected to said input terminal, its second terminal connected to said first terminals of said third and fourth transistors, and its third terminal connected to said applied voltage terminal; and said sixth transistor having its first terminal connected to said first terminal of said first and second transistors, its second terminal connected to said common voltage terminal, and its third terminal connected to said second terminal of said fifth transistor.

Claim 19

A current mirror circuit, comprising: an input terminal; an output terminal; an applied voltage terminal; a common voltage terminal; a first pair of transistors connected in parallel, current mirroring configuration to said common voltage terminal; a second pair of transistors connected in parallel cascoded configuration between respective ones of said input and output terminals and respective ones of said first pair of transistors; first voltage level shifting means connected between said applied voltage terminal and said second pair of transistors to control forward biasing of said second pair of transistors; said first voltage level shifting means comprising a third pair of transistors connected in series between said applied voltage terminal and said common voltage terminal; second voltage level shifting means connected between said applied voltage terminal and said first pair of transistors to control forward biasing of said first pair of transistors; said second voltage level shifting means comprising a fourth pair of transistors connected in series between said applied voltage terminal and said common voltage terminal; wherein each of said transistors has first, second and third terminals; said second and third terminals defining a current flow and said first terminal defining a contact for applying a voltage for controlling current flow through said current flow path; said first pair of transistors comprises first and second transistors having commonly connected first and second terminals; said second pair of transistors comprises third and fourth transistors having first terminals connected together, second terminals respectively connected to said third terminals of said first and second transistors and third terminals respectively connected to said input and output terminals; and said third pair of transistors comprises fifth and sixth transistors; said fifth transistor having its first terminal connected to said input terminal, its second terminal connected to said first terminals of said third and fourth transistors, and its third terminal connected to said applied voltage terminal; and said sixth transistor having its first terminal connected to said first terminal of said first and second transistors, its second terminal connected to said common voltage terminal, and its third terminal connected to said second terminal of said fifth transistor.

Claim 20

The circuit of claim 15, wherein said fourth pair of transistors comprises seventh and eighth transistors; said seventh transistor having its first terminal connected to said input terminal, its second terminal connected to first terminals of said first and second transistors, and its third terminal connected to said applied voltage terminal; and said eighth transistor having its first terminal connected to said first terminals of said first and second transistors, its second terminal connected to said common voltage terminal, and its third terminal connected to said second terminal of said seventh transistor.

Claim 21

The circuit of claim 16, wherein said eighth transistor has its first and third terminals connected together.

Claim 22

A current mirror circuit comprising: an input terminal; an output terminal; an applied voltage terminal; a common voltage terminal; first and second transistors having sources commonly connected to said common voltage terminal, gates commonly connected to each other, and drains; third and fourth transistors having sources respectively connected to said drains of said first and second transistors, gates commonly connected to each other, and drains respectively connected to said input and output terminals; first voltage level shifting circuitry connected between said applied voltage terminal and said common voltage terminal, for applying a forward biasing voltage at said common connection of said third and fourth transistor gates; and second voltage level shifting circuitry comprising a seventh transistor having a gate connected to said input terminal, a drain connected to said applied voltage terminal, and a source connected to said common connection of said first and second transistor gates; and an eighth transistor having a gate connected to said common connection of said first and second transistor gates, a drain connected to said source of said seventh transistor, and a source connected to said common voltage terminal.

Claim 23

A current mirror circuit comprising: an input terminal; an output terminal; an applied voltage terminal; a common voltage terminal; first and second transistors having sources commonly connected to said common voltage terminal, gates commonly connected to each other, and drains; third and fourth transistors having sources respectively connected to said drains of said first and second transistors, gates commonly connected to each other, and drains respectively connected to said input and output terminals; first voltage level shifting circuitry connected between said applied voltage terminal and said common voltage terminal, for applying a forward biasing voltage at said common connection of said third and fourth transistor gates; and second voltage level shifting circuitry comprising a seventh transistor having a gate connected to said input terminal, a drain connected to said applied voltage terminal, and a source connected to said common connection of said first and second transistor gates; and an eighth transistor having a gate connected to said common connection of said first and second transistor gates, a drain connected to said source of said seventh transistor, and a source connected to said common voltage terminal.