US5513375A
Expired / Lapsed
US
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System for compensating data rate between a storage device and a data compression processor using a buffer memory mapped twice into contiguous address space of a host processing unit
Assignee: Avid Technology Inc
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Filing: 1994-04-28
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Granted: 1996-04-30
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Expires: 2014-04-28
Abstract
Abstract A data buffer that compensates the differences in data rates, between a storage device and an image compression processor. A method and apparatus for the real time indexing of frames in a video data sequence.
Inventors
- 👤 Eric C. Peters
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:13
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G11; G11B; G11B27/00; G11B27/02; G11B27/031; G11B27/034; G11B27/10; G11B27/19; G11B27/28; H; H04; H04N; H04N19/00; H04N19/10; H04N19/102; H04N19/124; H04N19/126; H04N19/134; H04N19/146; H04N19/15; H04N19/152; H04N5/00; H04N5/76; H04N5/91; H04N5/92; H04N5/926; H04N5/9261; H04N5/9264; H04N7/00; H04N7/24; H04N9/00; H04N9/79; H04N9/80; H04N9/804; H04N9/8042; H04N19/50; H04N19/60; H04N5/84; H04N5/85; H04N5/907
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
102 words
A method for compensating for data rate differences between a storage device and a data compression processor and for transferring data between the storage device and the data compression processor, comprising the steps of: providing a data interface linking an addressable data buffer, a host processing unit, and the storage device, the host processing unit including an address space; and mapping the data buffer twice into the address space of the host processing unit, to provide a contiguous buffer memory; and transferring data between the data buffer and the storage device by passing the data through the host processing unit only once.
Claim 2
Independent Claim
102 words
A method for compensating for data rate differences between a storage device and a data compression processor and for transferring data between the storage device and the data compression processor, comprising the steps of: providing a data interface linking an addressable data buffer, a host processing unit, and the storage device, the host processing unit including an address space; and mapping the data buffer twice into the address space of the host processing unit, to provide a contiguous buffer memory; and transferring data between the data buffer and the storage device by passing the data through the host processing unit only once.
Claim 3
Dependent Claim
26 words
A method as claimed in claim 1, further comprising the step of direct memory access transferring the data from the data buffer to the compression processor.
Claim 4
Dependent Claim
25 words
A method as claimed in claim 1, further comprising the step of direct memory access transferring data from the compression processor to the data buffer.
Claim 5
Dependent Claim
34 words
The method according to claim 1, wherein the step of transferring the data between the compressed data buffer and the storage device is accomplished by placing the data on the data interface, only once.
Claim 6
Dependent Claim
46 words
The method according to claim 1, wherein the step of transferring the data between the storage device and the compressed data buffer is accomplished with only a single call to the host processing unit thereby resulting in only a single read operation from the storage device.
Claim 7
Dependent Claim
35 words
The method according to claim 5, wherein the single read operation may be initiated anywhere in the stored data, on the storage device, and need not be initiated at the beginning of the stored data.
Claim 8
Independent Claim
197 words
A system for compensating for data rate differences between a storage device and a data compression processor comprising: a host control processing unit including a bus having an address space and a local memory; an addressable compressed data buffer including a first port and a second port, the first port being coupled to the data compression processor wherein the data buffer is twice mapped into the address space of the host control processing unit to provide a contiguous buffer memory; a direct memory access address register connected to the data buffer, which stores data addresses of a location within the data buffer; a direct memory access limit register connected to the data buffer which limits a direct memory access transfer of data between the compression processor and the compressed data buffer; a data interface linking the second port of the data buffer, the host control processing unit, the local memory and the storage device; whereby a data transfer between the storage device and the addressable compressed data buffer is accomplished by passing the data through the host control processing unit only once, and without storing the data in the local memory of the host control processing unit.
Claim 9
Independent Claim
197 words
A system for compensating for data rate differences between a storage device and a data compression processor comprising: a host control processing unit including a bus having an address space and a local memory; an addressable compressed data buffer including a first port and a second port, the first port being coupled to the data compression processor wherein the data buffer is twice mapped into the address space of the host control processing unit to provide a contiguous buffer memory; a direct memory access address register connected to the data buffer, which stores data addresses of a location within the data buffer; a direct memory access limit register connected to the data buffer which limits a direct memory access transfer of data between the compression processor and the compressed data buffer; a data interface linking the second port of the data buffer, the host control processing unit, the local memory and the storage device; whereby a data transfer between the storage device and the addressable compressed data buffer is accomplished by passing the data through the host control processing unit only once, and without storing the data in the local memory of the host control processing unit.
Claim 10
Dependent Claim
19 words
The system set forth in claim 7, where the data buffer is configured to store digital video image data.
Claim 11
Dependent Claim
19 words
The system set forth in claim 8, where the compression processor is configured to compress digital video image data.
Claim 12
Dependent Claim
59 words
The system set forth in claim 8, where the compression processor is configured to compress image data by: computing a discrete transform of the image data to create a plurality of coefficients corresponding to frequencies; quantizing the plurality of coefficients to create a plurality of quantized coefficients; and coding the quantized coefficients to create a plurality of encoded coefficients.
Claim 13
Dependent Claim
30 words
The system according to claim 7, wherein the data is transferred between the storage device and the addressable compressed data buffer by placing the data on the interface only once.
Claim 14
Dependent Claim
51 words
The system according to claim 7, wherein the data is transferred between the storage device and the addressable compressed data buffer by reading the data, from the storage device, with only a single call to the host processing unit, thereby resulting in only a single read operation of the storage device.
Claim 15
Dependent Claim
31 words
The system according to claim 12, wherein the single read operation may be started anywhere in the stored data and need not be started at a beginning of the stored data.
Claim 16
Dependent Claim
38 words
The system according to claim 7, wherein the host control processing unit further comprises a central processing unit, coupled to the data interface, which controls the data transfer between the storage device and the addressable compressed data buffer.
Claim 17
Independent Claim
93 words
A system for transferring data between a data compression processor and a storage device, comprising: a controller unit including a bus having an address space; an addressable compressed data buffer which is twice mapped into the address space of the controller unit to provide a contiguous buffer memory; a data interface linking the addressable compressed data buffer, the controller unit, the storage device and the compression processor; and whereby a data transfer between the storage device and the data compression processor is accomplished by passing the data through the controller unit only once.
Claim 18
Independent Claim
93 words
A system for transferring data between a data compression processor and a storage device, comprising: a controller unit including a bus having an address space; an addressable compressed data buffer which is twice mapped into the address space of the controller unit to provide a contiguous buffer memory; a data interface linking the addressable compressed data buffer, the controller unit, the storage device and the compression processor; and whereby a data transfer between the storage device and the data compression processor is accomplished by passing the data through the controller unit only once.
Claim 19
Dependent Claim
30 words
The system according to claim 15, wherein the data is transferred between the storage device and the data compression processor by placing the data on the data interface only once.
Claim 20
Dependent Claim
49 words
A system according to claim 15, wherein the data is transferred between the storage device and the data compression processor by reading the data, from the storage device with only a single call to the controller unit, thereby resulting in only a single read operation of the storage device.
Claim 21
Dependent Claim
31 words
A system according to claim 17, wherein the single read operation may be started anywhere in the stored data and need not be started at a beginning of the stored data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-30 | 1999-10-30 | 2000-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-30 | 2003-10-30 | 2004-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-30 | 2007-10-30 | 2008-04-30 | $7700.00 | Window Closed / Lapsed |