EP0185924A2
Expired / Lapsed
EP
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Buffer system with detection of read or write circuits' failures
Assignee: International Business Machines Corp
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Filing: 1985-11-19
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Granted: —
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Expires: 2005-11-19
Abstract
Abstract An improved data buffer has a storage tray (14) that is addressable for read and write operations by an address of n bits that are supplied by a read address counter (16) and a write address counter (18) which each have n+1 bits. The (n+1)th bit is in effect a modulo-2 counter for passes through the array by the read and write circuits. During a write operation the (n+1)th bit (44) of the write counter (18) is stored as part of a parity bit (P) for the addressed array location. During a read operation the (n+1)th bit (51) of the read address counter (16) is entered into a parity checking function (30) on the word read (25) from the addressed location. An error is signalled if the (n+1)th bit of the read address counter does not agree with the (n + 1)th bit of the write counter at the time of the write operation. For example, an error is detected if the write circuits fail and the read circuits make a second pass through words that have not previously been read. This prevents reading the same entries on a next pass through the array (14).
Inventors
- 👤 Daniel F. Casper
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 14:06
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/78; G06F7/785; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076; G06F5/00; G06F5/06; G06F5/10
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
283 words
A buffer memory system (12) for transmitting a succession of data words between components (34, 37) of a data processing system, comprising: a memory array (14) having 2 n storage locations (56) addressable by an address of n bits, means for accessing the buffer as a circular queue, said accessing means including a modulo-2 n write address counter (18), means (57, 39) for forming the parity of data to be stored, means (22, 14) for storing a data word and a parity bit at the location (56) of the write address counter, and means (40) for incrementing the write address counter for successive write operations, a modulo-2 n read address counter (16), means (14, 25) for reading a data word from the location of the read address counter, means (41)-for incrementing the read address counter, and means (58) for checking parity of a data word on a read operation and signalling an error or the absence of an error t characterized by: means (44, 51) for identifying alternate passes through the write address counter (18) and through the read address counter (16) as odd and even, means (27) operable on a word going to be written during an odd write pass to form and write an odd parity bit and during an even write pass to form and write an even parity bit, and means (30) operable on a word read during an odd read pass to check odd parity and operable during an even read pass to check even parity, whereby a parity error will be signalled also in case the read operation does not proceed in the same parity sequence as did the write operation when writing the word now read.
Claim 2
Dependent Claim
283 words
A buffer memory system (12) for transmitting a succession of data words between components (34, 37) of a data processing system, comprising: a memory array (14) having 2 n storage locations (56) addressable by an address of n bits, means for accessing the buffer as a circular queue, said accessing means including a modulo-2 n write address counter (18), means (57, 39) for forming the parity of data to be stored, means (22, 14) for storing a data word and a parity bit at the location (56) of the write address counter, and means (40) for incrementing the write address counter for successive write operations, a modulo-2 n read address counter (16), means (14, 25) for reading a data word from the location of the read address counter, means (41)-for incrementing the read address counter, and means (58) for checking parity of a data word on a read operation and signalling an error or the absence of an error t characterized by: means (44, 51) for identifying alternate passes through the write address counter (18) and through the read address counter (16) as odd and even, means (27) operable on a word going to be written during an odd write pass to form and write an odd parity bit and during an even write pass to form and write an even parity bit, and means (30) operable on a word read during an odd read pass to check odd parity and operable during an even read pass to check even parity, whereby a parity error will be signalled also in case the read operation does not proceed in the same parity sequence as did the write operation when writing the word now read.
Claim 3
Dependent Claim
197 words
A buffer system according to claim 1, further comprising: a cycle of one of said address counters (16, 18) corresponding to a pass through the array by the read circuits or write circuits, an improvement for detecting errors caused by faults in said read or write circuits, comprising: additional bit position means (n+1) in said write counter (18) for counting passes through the array by said write circuits and additional bit position means (n+1) in said read counter (16) for counting passes through the array by said read circuits, means for beginning a data transfer with the value of the read pass count (51) set according to the write pass count (44), bit position means (P) in each storage location (56) of the array (14) and means (44, 27, 46, 22) for entering a function of the write pass count into said bit position means of a storage location addressed for a write operation, and means (30, 40, 58) for comparing the pass count (51) of the read address counter (16) with the write pass count in a word (25) read from the array and for signalling (62) an error if said counts do not compare equal.
Claim 4
Dependent Claim
57 words
The buffer system of Claim 2 wherein said additional bit position means in each of said counters comprises one bit position (n+1). and said means (44, 27, 46, P in 22) for entering and storing a function of the write pass count further comprises one bit position (P) in each storage location (56) of the array (14).
Claim 5
Dependent Claim
43 words
The buffer system of Claim 3 wherein said array is addressable by an address of n bits, said counters each comprise n bit positions of lower order designated 1 through n for the address and a bit position (n+1) for said pass count.
Claim 6
Dependent Claim
184 words
The buffer system of Claim 2, 3 or 4 wherein data entering (34) the buffer system has a parity bit (39) and data leaving (37) the buffer system has a parity bit (40), and wherein said write circuits include means (P) for forming a parity bit for data (22) to be stored in a storage location, further comprising: means (27, 46) in said write circuits for forming said function of the write pass count as the combined parity of said data parity (39) and the (n+l)th bit (44) of the write address counter (18), and means (30) in said read circuits for forming a parity bit (40) for data leaving (37) the array (14) as a function of the parity (47) of a word read (25) from the array and the (n+l)th bit (51) of the read address counter, and means (58) for checking the data leaving the array, including the data part (37) and the parity bit (40), whereby a mismatch between the write pass count parity (44) and the read pass count parity (51) produces a parity error (62) in the data.
Claim 7
Dependent Claim
67 words
The buffer system of Claim 5 including means for setting said read address counter according to the value of the write address counter at the beginning of an operation, whereby the said address sequence is continued from one data transfer operation to the next without reset to a fixed starting value and consecutive passes through the array have different count values in the read and write counters.
References Cited (Backward Citations)
No citation records indexed.
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