US4599689A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Continuous data transfer system
Assignee: Data Translation Inc
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Filing: 1983-02-28
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Granted: 1986-07-08
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Expires: 2003-02-28
Abstract
Abstract Apparatus controls sequential direct memory access (DMA) transfers between a plurality of buffer memories and a data translation device. Each buffer memory has an overrun area associated with it. Prior to transfers from the buffer memories to the data translation device, the buffer memories are first "threaded" together by loading the overrun area of a first buffer memory with data from the next buffer memory. During the DMA transfer, when the first buffer memory becomes empty a request is made to a computer to restart the DMA operation on the next sequential buffer, but while the request is being serviced, data is continually being transferred out of the first buffer's overrun area. Alternatively, for transfers from the data translation device to the buffer memories, after the first buffer memory is full, an interrupt is generated and incoming data is stored in the first buffer memory's overrun area while the interrupt is being serviced. After the interrupt is serviced, data is stored in the next sequential buffer memory in an area offset from the beginning thereof equal to the overrun area filled with data, the computer determining the exact point where the DMA process stopped depositing data in the overrun area by sequentially examining the entries in the overrun area. The computer then moves the data in the overrun area into the next buffer to complete the transfer.
Inventors
- 👤 Ari P. Berman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:40
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
212 words
Computer apparatus for continuously transferring data words from a peripheral unit to a plurality of buffer memories, each of said buffer memories having a plurality of storage locations for storing a predetermined number of data words, said apparatus comprising, plurality of overrun memories, each of said overrun memories having a predetermined number of storage locations and being assigned to one of said plurality of buffer memories, means for sequentially transferring data words from said peripheral unit to sequential storage locations in a first one of said buffer memories, said transferring means transferring words to sequential storage locations in said overrun memory assigned to said first buffer memory when said first buffer memory is filled with data words, means for counting the number of data words transferred by said transferring means to said first buffer memory and said overrun memory, said counting means generating an interrupt signal when said first buffer memory becomes filled with data words, means responsive to said interrupt signal for controlling said transfer means to transfer data words from said peripheral unit to a second one of said buffer memories starting at a location spaced from the beginning of said second buffer memory a number of locations equal to the number of data words stored in said overrun area.
Claim 2
Dependent Claim
212 words
Computer apparatus for continuously transferring data words from a peripheral unit to a plurality of buffer memories, each of said buffer memories having a plurality of storage locations for storing a predetermined number of data words, said apparatus comprising, plurality of overrun memories, each of said overrun memories having a predetermined number of storage locations and being assigned to one of said plurality of buffer memories, means for sequentially transferring data words from said peripheral unit to sequential storage locations in a first one of said buffer memories, said transferring means transferring words to sequential storage locations in said overrun memory assigned to said first buffer memory when said first buffer memory is filled with data words, means for counting the number of data words transferred by said transferring means to said first buffer memory and said overrun memory, said counting means generating an interrupt signal when said first buffer memory becomes filled with data words, means responsive to said interrupt signal for controlling said transfer means to transfer data words from said peripheral unit to a second one of said buffer memories starting at a location spaced from the beginning of said second buffer memory a number of locations equal to the number of data words stored in said overrun area.
Claim 3
Dependent Claim
51 words
Computer apparatus according to claim 1 further comprising means operable after said transferring means begins transferring data words to said second one of said buffer memories for moving data words stored in said overrun memory assigned to said first buffer memory to locations at the begining of said second buffer memory.
Claim 4
Dependent Claim
52 words
Computer apparatus according to claim 2 further comprising means operable prior to data word transfers from said peripheral unit to said buffer memories for storing a predetermined code word in all locations of all of said overrun memories, said code word consisting of a code which cannot appear in said data words.
Claim 5
Dependent Claim
57 words
Computer apparatus according to claim 3 wherein said moving means comprises means responsive to data words stored in said overrun memory for comparing each of said data words to said predetermined code word and means controlled by said comparing means for moving each data word which does not match said code word to said second buffer memory.
Claim 6
Dependent Claim
272 words
Computer apparatus for continuously transferring data words from an ordered sequence of buffer memories to a peripheral unit, each of said buffer memories having a plurality of storage locations for storing a predetermined number of data words, said apparatus comprising, a plurality of overrun memories, each of said overrun memories having a predetermined number of storage locations and being assigned to one of said plurality of buffer memories, means for sequentially transferring data words from sequential locations in a first one of said buffer memories to said peripheral unit, said transferring means including means for transferring information to said overrun memory associated with said first buffer memory from a second one of said buffer memories immediately following said first buffer memory in said ordered sequence until said overrun memory is filled with data words, means for transferring data words from sequential storage locations in said overrun memory assigned to said first buffer memory to said peripheral device when said first buffer memory is empty of data words, means for counting the number of data words transferred by said transferring means from said first buffer memory and said overrun memory, said counting means generating an interrupt signal when said first buffer memory becomes empty of data words, and means responsive to said interrupt signal for controlling said transfer means to transfer data words said peripheral unit from said second one of said buffer memories starting at a location spaced from the beginning of said second memories buffer a number of locations equal to the number of data words transferred by said transferring means from said overrun memory associated with said first buffer memory.
Claim 7
Dependent Claim
272 words
Computer apparatus for continuously transferring data words from an ordered sequence of buffer memories to a peripheral unit, each of said buffer memories having a plurality of storage locations for storing a predetermined number of data words, said apparatus comprising, a plurality of overrun memories, each of said overrun memories having a predetermined number of storage locations and being assigned to one of said plurality of buffer memories, means for sequentially transferring data words from sequential locations in a first one of said buffer memories to said peripheral unit, said transferring means including means for transferring information to said overrun memory associated with said first buffer memory from a second one of said buffer memories immediately following said first buffer memory in said ordered sequence until said overrun memory is filled with data words, means for transferring data words from sequential storage locations in said overrun memory assigned to said first buffer memory to said peripheral device when said first buffer memory is empty of data words, means for counting the number of data words transferred by said transferring means from said first buffer memory and said overrun memory, said counting means generating an interrupt signal when said first buffer memory becomes empty of data words, and means responsive to said interrupt signal for controlling said transfer means to transfer data words said peripheral unit from said second one of said buffer memories starting at a location spaced from the beginning of said second memories buffer a number of locations equal to the number of data words transferred by said transferring means from said overrun memory associated with said first buffer memory.
Claim 8
Dependent Claim
91 words
Computer apparatus according to claim 5 wherein said means for transferring information to said overrun memory comprises a counter, means for initially setting said counter to a predetermined count, means responsive to each transfer of a data word from said second one of said buffer memories to said overrun memory for decrementing said counter and means responsive to the count remaining in said counter for stopping the transfer of data words from said second one of said buffer memories to said overrun memory when said count reaches a second predetermined number.
Claim 9
Dependent Claim
28 words
Computer apparatus according to claim 5 wherein said means for transferring data words from said first buffer memory to said peripheral unit comprises a direct memory access circuit.
Claim 10
Dependent Claim
62 words
Computer apparatus according to claim 7 wherein said direct memory access circuit transfers data words from said overrun memory associated with said first buffer memory to said peripheral unit after said interrupt signal has been generated, but before said controlling means controls said transfer means to start transferring data words from said second one of said buffer memories to said peripheral unit.
Claim 11
Dependent Claim
97 words
Computer apparatus according to claim 7 wherein said direct memory access circuit comprises a register for storing a starting address and means for transferring data words located at said starting address and sequential locations and said controlling means comprises means responsive to said interrupt signal for setting said starting address in said register to the address of a location spaced from the beginning of said second one of said buffer memories a number of locations equal to the number of data words transferred by said transferring means from said overrun memory associated with said first buffer memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-07 | 1990-01-06 | 1990-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-07 | 1994-01-06 | 1994-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-07 | 1998-01-06 | 1998-07-08 | $7700.00 | Window Closed / Lapsed |