Patent US5508638A successfully refreshed from Google Patents.
US5508638A
Expired / Lapsed
US
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Low current redundancy fuse assembly
Assignee: Micron Technology Inc
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Filing: 1995-05-26
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Granted: 1996-04-16
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Expires: 2015-05-26
Abstract
Abstract In a microcircuit device such as a memory chip, where a bank of fuse-controlled latch pulse routing-circuits are used to program redundant circuits or other programming options with every memory cycle or multiple thereof, the amount of current drawn by every fuse-control circuit is reduced by controlling each bank of circuits with a bank-enabling, fuse-programmed circuit between the latch pulse source and the bank of fuse-controlled programing circuits, and by adding a second fuse into each programing circuit; whereby, the bank of programming circuits can be enabled by alternately blowing one of two fuses in the bank-enabling circuit, and each programming logic can set by alternately blowing one of its pair of fuses thus cutting off any current path through the programing circuit regardless of the programing state of the circuit.
Inventors
- 👤 Timothy B. Cowles
- 👤 Steven G. Renfro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:26
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C29/787; G11C29/83; G11C29/832; H; H03; H03K; H03K19/00; H03K19/003; H03K19/00392; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
70 words
A bank of programming logic circuits for enabling and disabling elements of an array of microcircuit devices, wherein each of said programming logic circuits comprises: first and second fuses and a switching transistor wired in series, each of said fuses having a status; and means for detecting the status of said fuses, said means for detecting comprising an output signal taken at a point between said first and second fuses.
Claim 2
Dependent Claim
70 words
A bank of programming logic circuits for enabling and disabling elements of an array of microcircuit devices, wherein each of said programming logic circuits comprises: first and second fuses and a switching transistor wired in series, each of said fuses having a status; and means for detecting the status of said fuses, said means for detecting comprising an output signal taken at a point between said first and second fuses.
Claim 3
Dependent Claim
66 words
The bank of claim 1, wherein said means for detecting further comprise: a first pole of a supply voltage; a second pole of said supply voltage; and a control line; wherein said switching transistor has a first current-carrying terminal connected to said first pole, a second current-carrying terminal wired to a first terminal of said first fuse, and a control terminal wired to said control line.
Claim 4
Dependent Claim
19 words
The bank of claim 2, wherein a second terminal of said second fuse is wired to said second pole.
Claim 5
Dependent Claim
26 words
The bank of claim 3, wherein said point is wired to a second terminal of said first fuse and a first terminal of said second fuse.
Claim 6
Dependent Claim
206 words
A bank of programming logic circuits for enabling and disabling elements of an array of microcircuit devices, wherein each of said programming logic circuits comprises: first and second fuses wired in series, each of said fuses having a status; and means for detecting the status of said fuses, said means for detecting comprising: an output signal taken at a point between said first and second fuses; a first pole of a supply voltage; a second pole of said supply voltage; a control line; switching means, responsive to a first signal appearing on said control line, for applying a voltage appearing on said first pole to a first terminal of said first fuse; wherein said switching means comprise a switching transistor having a first current-carrying terminal connected to said first pole, a second current-carrying terminal wired to said first terminal of said first fuse, and a control terminal wired to said control line; wherein a second terminal of said second fuse is wired to said second pole; wherein said point is wired to a second terminal of Said first fuse and a first terminal of said second fuse; and wherein each of said logic circuits further comprises a programming driver having an input connected to said point.
Claim 7
Dependent Claim
206 words
A bank of programming logic circuits for enabling and disabling elements of an array of microcircuit devices, wherein each of said programming logic circuits comprises: first and second fuses wired in series, each of said fuses having a status; and means for detecting the status of said fuses, said means for detecting comprising: an output signal taken at a point between said first and second fuses; a first pole of a supply voltage; a second pole of said supply voltage; a control line; switching means, responsive to a first signal appearing on said control line, for applying a voltage appearing on said first pole to a first terminal of said first fuse; wherein said switching means comprise a switching transistor having a first current-carrying terminal connected to said first pole, a second current-carrying terminal wired to said first terminal of said first fuse, and a control terminal wired to said control line; wherein a second terminal of said second fuse is wired to said second pole; wherein said point is wired to a second terminal of Said first fuse and a first terminal of said second fuse; and wherein each of said logic circuits further comprises a programming driver having an input connected to said point.
Claim 8
Dependent Claim
329 words
A circuit for enabling and disabling elements of a microcircuit array comprises: a plurality of programming logic circuits; a bank enabling circuit; a latch pulse source; a supply voltage source; a circuit ground reference; wherein said bank enabling circuit comprises: a bank output line; a first bank fuse, having a first terminal and a second terminal; a second bank fuse, having a first terminal and a second terminal; a bank switching transistor having a first current-carrying terminal, a second current-carrying terminal and a control terminal; wherein said first terminal of said bank transistor is connected to said supply voltage source; said second terminal of said bank transistor is connected to said first terminal of said first bank fuse; said control terminal of said bank transistor is connected to said latch pulse source; said second terminal of said first bank fuse is connected to said first terminal of said second bank fuse; said second terminal of said second bank fuse is connected to said ground reference; said bank output line is connected to said second terminal of said first bank fuse; wherein each of said programming logic circuits comprises: a control input line connected to said bank output line; a status output line; a first fuse, having a first terminal and a second terminal; a second fuse, having a first terminal and a second terminal; a switching transistor having a first current-carrying terminal, a second current-carrying terminal and a control terminal; wherein said first terminal of said first fuse is connected to said supply voltage source; said second terminal of said first fuse is connected to said first terminal of said second fuse; said second terminal of said second fuse is connected said first terminal of said switching transistor; said second terminal of said switching transistor is connected to said ground reference; said control input line is connected to said control terminal of said switching transistor; and said status output line is connected to second terminal of said first fuse.
Claim 9
Dependent Claim
329 words
A circuit for enabling and disabling elements of a microcircuit array comprises: a plurality of programming logic circuits; a bank enabling circuit; a latch pulse source; a supply voltage source; a circuit ground reference; wherein said bank enabling circuit comprises: a bank output line; a first bank fuse, having a first terminal and a second terminal; a second bank fuse, having a first terminal and a second terminal; a bank switching transistor having a first current-carrying terminal, a second current-carrying terminal and a control terminal; wherein said first terminal of said bank transistor is connected to said supply voltage source; said second terminal of said bank transistor is connected to said first terminal of said first bank fuse; said control terminal of said bank transistor is connected to said latch pulse source; said second terminal of said first bank fuse is connected to said first terminal of said second bank fuse; said second terminal of said second bank fuse is connected to said ground reference; said bank output line is connected to said second terminal of said first bank fuse; wherein each of said programming logic circuits comprises: a control input line connected to said bank output line; a status output line; a first fuse, having a first terminal and a second terminal; a second fuse, having a first terminal and a second terminal; a switching transistor having a first current-carrying terminal, a second current-carrying terminal and a control terminal; wherein said first terminal of said first fuse is connected to said supply voltage source; said second terminal of said first fuse is connected to said first terminal of said second fuse; said second terminal of said second fuse is connected said first terminal of said switching transistor; said second terminal of said switching transistor is connected to said ground reference; said control input line is connected to said control terminal of said switching transistor; and said status output line is connected to second terminal of said first fuse.
Claim 10
Dependent Claim
25 words
The circuit of claim 6, wherein each of said logic circuits further comprises a programming driver having an input connected to said status output line.
Claim 11
Dependent Claim
37 words
The circuit of claim 6, wherein said bank enabling circuit further comprises a current driver having an input terminal connected to said bank output line and an output terminal connected to each of said programming logic circuits.
Claim 12
Dependent Claim
20 words
The circuit of claim 6, wherein each of said programming logic circuits is connected to an array of microcircuit devices.
Claim 13
Dependent Claim
19 words
The circuit of claim 6, wherein each of said programming logic circuits is connected to a microcircuit memory array.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-16 | 1999-10-16 | 2000-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-16 | 2003-10-16 | 2004-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-16 | 2007-10-16 | 2008-04-16 | $7700.00 | Window Closed / Lapsed |