Pipeline processor with hardware loop function using instruction address stack for holding content of program counter and returning the content back to program counter

Claim 1

A pipeline processor having a hardware loop function, comprising: an instruction pipeline processing unit which has at least one input stage and at least one output stage; an instruction memory which stores instructions, including a loop start instruction for starting a loop processing and a loop terminating instruction for terminating the loop processing, to be inputted to the input stage of said instruction pipeline processing unit; a program counter which outputs an instruction address for specifying an instruction to be inputted from said instruction memory to said instruction pipeline processing unit; an instruction address stack which selectively holds content from said program counter, and can return said content back to said program counter when loop processing is started by said loop start instruction; a loop counter to which an initial value of loop times is set, and which can be decremented; a loop control unit which sets the initial value of loop times into said loop counter when said instruction pipeline processing unit executes said loop start instruction, and said loop control unit detects whether a current value of said loop counter is a predetermined value or not when said instruction pipeline processing unit executes said loop terminating instruction, returns the content of said instruction address stack to said program counter and decrements the current value of said loop counter when a detection result is other than the predetermined value, and terminates the loop processing when the detection result is the predetermined value; an operation executing unit which executes operations according to the instructions outputted from the output stage of said instruction pipeline processing unit; and a flag register which is selectively set with contents according to result of the operations executed by said operation executing unit; the pipeline processor further comprising: a transfer path which transfers the contents set in said flag register to said loop control unit; wherein said loop control unit reads said flag register via said transfer path when said instruction pipeline processing unit executes said loop terminating instruction, and terminates the loop processing when the contents set in said flag register are the predetermined value.